View SAA7391_139753.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAA7391 ATAPI CD-R block encoder/decoder
Objective specification File under Integrated Circuits, IC01 1997 Aug 01
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
CONTENTS 1 2 2.1 2.2 2.3 2.4 2.5 2.6 3 4 5 6 6.1 7 7.1 7.1.1 7.2 7.2.1 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.4.1 7.4.2 7.4.3 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 FEATURES GENERAL DESCRIPTION Memory mapped control registers Error correction features Host interface features Buffer memory organisation Subcode handling features Multimedia output audio control features QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING Detailed description of pin functions FUNCTIONAL DESCRIPTION Memory field description DVD-ROM memory field information CD input control registers Registers associated with data in process Multimedia output interface Subcode input block Subcode mode transmit control register General description of the multimedia output interface IEC 958/EBU output Memory-to-memory block copy function Interrupt registers Interrupt 1 Interrupt 2 UART interrupt Host interface Introduction Description of the host interface block Description of the host interface registers Transfer counter Packet size store Sequencer status Host interface DMA special bits Automatic block pointer reload programming DMA transfer programming of the host interface Generic interface operation 7.6 7.6.1 7.6.2 7.7 7.7.1 7.7.2 7.7.3 7.8 7.8.1 7.9 7.9.1 7.10 7.10.1 7.10.2 7.10.3 8 9 10 11 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.3 11.4 12 13 14 15 15.1 15.2 15.3 15.4 16 17 7.5.11 7.5.12 7.5.13
SAA7391
DMA transfers in generic mode Normal DMA mode Burst DMA mode using multiplexed bus configuration Microcontroller interface Kernel based firmware 16-bit registers automatic read and write 8051 CPU and memory management functions Sub-CPU bus access timing Buffer memory organisation Subpage External memory interface DRAM interface configuration register UART for communication with CD engine UART basic engine interface Clock generation control Crystal oscillator Sub-CPU clock control register SAA7391 system clock control registers LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING CHARACTERISTICS External memory interface timing Host interface timing Host interface ATAPI PIO and DMA timing ATA bus timing Ultra DMA operation and timing Ultra DMA read/write timing Sub-CPU interface timing UART timing APPENDIX A APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
1997 Aug 01
2
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
1 FEATURES
SAA7391
The reading and writing of 16-bit registers within the device can be performed by two separate 8-bit reads, where the second byte data is latched at the same time as the first byte is read. 2.2 Error correction features
* Supports real time error detection and correction in hardware. Error correction to n = 27, error detect to n = 30 and raw data transfer to n = 32. * CD-R to CD-n greater than 8. Internal operation is faster, but firmware and physical (laser/media) factors limit the speed * DVD-ROM supported in combination with the SAA7335 * Direct generic interface to external Small Computer Systems Interface (SCSI) controller devices * Operates with up to 16 Mbytes DRAM - Hyper-page DRAM up to 33 Mbytes words/s burst - Fast-page DRAM at up to 17.5 Mbytes words/s burst * Has fixed n = 1 or n = 2 rate (44.1 or 88.2 kHz) I2S-bus multimedia output for simple audio/video output; features for CAV/quasi-CLV support - Supports Philips multimedia audio CODEC - Provides `SHOARMA' Red Book audio buffer * IEC 958 (SPDIF, AES/EBU and DOBM) output with Q-W subcode and programmable category code, output at n = 1 rate * Device registers are memory mapped for faster direct access to the chip * Provides direct access from sub-CPU to buffer RAM to support scratchpad accesses. This eliminates the need for extra RAM chips in the system * Automatic sequencing of ATAPI packet command protocol, including command termination * Automated data transfers to and from the host using PIO, DMA and ultra DMA. 2 GENERAL DESCRIPTION
The SAA7391 has an on-chip 36 kbits memory that is used as a buffer memory for error and erasure correction processing. This buffer memory reduces the number of external RAM accesses that are needed for error correction and thus allows for an increased rate of data throughput. The error corrector is switchable between two-pass, single-pass [both with Error Detection/Correction (EDC)] and EDC only modes to further improve throughput. The presence of the full error corrector removes the need for firmware based control of the error corrector's operation. 2.3 Host interface features
The SAA7391 has an ATAPI host interface that may be directly connected to the ATAPI bus thereby reducing the need for external support devices. It supports PIO Mode 4 transfer and Mode 0 ultra DMA. This interface can also be configured as a generic DMA interface for use with external host interface devices (e.g. SCSI controller). The DMA interface has the following features: * ATAPI command packets are automatically loaded into the command FIFO * Data transfer to the host is automatically sequenced to reduce inter-block latencies and improve host CPU utilisation * Host data transfer rate is independent of error corrector operation and the data input path * The host interface features automatic determination of block length for Mode 2, Form 1 and Form 2 sectors. The block length transferred is programmable. * The host interface can transfer up to 3 sub-blocks per sector, with each sub-block being transferred dependent on the Form bit. Automatic reload of sub-block pointers and unconditional transfer are supported.
The SAA7391 is a block decoder/encoder and buffer manager for high-speed CD-ROM/CD-R functions, that integrates real time error correction and detection and bidirectional ATAPI transfer functions into a single chip. 2.1 Memory mapped control registers
The SAA7391 device has a large number of memory mapped registers. These are arranged so that high-level languages see the registers as external byte or 16-bit integer quantities. The block addressing of the SAA7391 facilitates the use of pairs of 16-bit quantities to represent addresses.
1997 Aug 01
3
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
2.4 Buffer memory organisation
SAA7391
* Subcodes are written into memory together with their associated sector data.This eases the provision of specialist features, for example CD + G or Karaoke CD applications. * All channels of subcode are de-interleaved * The Q channel is also Cyclic Redundancy Checked (CRC) for increased reliability * When operating in 3-wire subcode mode, it is possible to control or read the P bit in the P-W subcode stream. 2.6 Multimedia output audio control features
Memory is mapped as a 16-bit block number and 12-bit offset into that block. The block oriented memory structure permits the use of 16-bit pointers in software thereby minimising the overhead of accessing memory. The address can be found from the following equation: address = block number x 2560 + offset. The microcontroller sees the SAA7391 as a memory mapped peripheral, with control and status registers appearing in the upper address space. The lowest 52 kbytes (48 kbytes + 4 kbytes) of the 8051 microcontroller external address space is mapped as a window into the memory on a user-specified 1 kbyte boundary within the buffer RAM. This can be used as a scratchpad memory. The next 4 kbytes is separately mapped as a window into the memory on a user-specified 1 kbyte boundary within the RAM. The next 7.5 kbytes of the external data space consists of three independently addressed memory segments for accessing block data, subcode information and block headers. The registers of the SAA7391 are mapped into the top 256 bytes of external data space. 2.5 Subcode handling features
The I2S-bus input may be processed before feeding to the multimedia audio output in several simple ways: * As audio is transferred via the buffer memory, it is not necessary to have the CD-DSP I2S-bus input at exactly the audio n = 1 or video n = 2 rate. Any faster speed will work because the buffer RAM is used as a FIFO. * Both channels may be independently controlled. The left channel output may be sourced from zero (digital silence), left or right input; this also applies for the right channel output. This permits basic audio switching and channel swapping. * IEC 958 (SPDIF, AES/EBU and DOBM) output with Q-W subcode and programmable category code, can be output from the same CD-DSP I2S-bus data source.
The writing of data into the buffer RAM is aligned to the absolute time sync marker with the following features: 3 QUICK REFERENCE DATA SYMBOL VDDD(core) VDDD(pad) IDDD fxtal Tamb Tstg 4 PARAMETER digital core supply voltage digital peripheral supply voltage supply current crystal frequency operating ambient temperature storage temperature 3.0 VDDD(core) tbf 8 0 -55 MIN. 3.3 5.0 or 3.3 60 8.4672, 16.9344 or 33.8688 - - TYP. MAX. 3.6 5.0 tbf 35 70 +125 UNIT V V mA MHz C C
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME LQFP144 DESCRIPTION plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm 4 VERSION SOT486-1
SAA7391H
1997 Aug 01
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
5 BLOCK DIAGRAM
SAA7391
handbook, full pagewidth
EXTERNAL DRAM
I2S-bus to CD-R I2S-bus from CD-DSP
DRIVE INTERFACE
ENCODER
ERROR CORRECTOR
MEMORY PROCESSOR
ATAPI HOST INTERFACE
IDE-bus
subcode to CD-R subcode from CD-DSP I2S-bus to DAC IEC 958
SUBCODE INTERFACE
SAA7391
MULTIMEDIA INTERFACE SYSTEM CLOCK GENERATOR TEST CONTROL BLOCK SUB-CPU INTERFACE
MGK506
master clock
clock
sub-CPU
Fig.1 The SAA7391 internal block diagram.
1997 Aug 01
5
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
6 PINNING SYMBOL n.c. n.c. XDA0 XDA1 XDA2 VDDD(pad6) DGND1 XDA3 XDA4 XDA5 XDA6 XDA7 XDA8 XDA9 XDA10 XDA11 DGND2 XRAS XCAS XWR XDD0 XDD1 VDDD(core1) DGND3 XDD2 XDD3 XDD4 XDD5 XDD6 XDD7 VDDD(pad7) DGND4 SCKI1 WSI1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 TYPE - - O O O - - O O O O O O O O O - O O O I/O I/O - - I/O I/O I/O I/O I/O I/O - - I I DRIVE/ THRESHOLD - - M M M - - M M M M M M M M M - H H H M/T M/T - - M/T M/T M/T M/T M/T M/T - - C C - - I2S-bus I/O - - RAM digital core supply voltage 1 digital ground 3 data bus input/output RAM - RAM digital ground 2 - - RAM GROUPING - - RAM not connected not connected output address lines
SAA7391
DESCRIPTION
digital peripheral supply voltage 6 digital ground 1 output address lines
row address strobe output (active LOW) column address strobe output (active LOW) write enable output (active LOW) data bus input/output
digital peripheral supply voltage 7 digital ground 4 I2S-bus bit clock input I2S-bus word select strobe input
1997 Aug 01
6
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL n.c. SDI1 SDO1 SFSY RCK SUBI SUBO CFLG C2P0 DGND5 IECO MCK
PIN 35 to 38 39 40 41 42 43 44 45 46 47 48 49
TYPE - I O I/O I/O I O I I - O I/O
DRIVE/ THRESHOLD - C M L/C L/C C L C C - M M/C
GROUPING - I2S-bus I/O not connected
DESCRIPTION
data input from CD engine data output to CD-R writer
subcode I/O
3-wire subcode sync input/output 3-wire subcode clock input/output Q and R-W subcode input subcode output from encoder to writer
I2S-bus input
CD error corrector flags and absolute time sync CD C2 error correction flag input for ERCO digital ground 5 IEC 958 output 256fs or 384fs clock for multimedia master clock/IEC 958 clock or divided system clock for CD-DSP I2S-bus bit clock input/output I2S-bus word select strobe input/output I2S-bus data output to DAC/video decoder
- multimedia multimedia output multimedia
SCK2 WS2 SDO2 GND CROUT CRIN VDDA Iref POR TEST1 TEST2 RESET DD7 DD8 DD6 VDDD(pad1) DGND6 DD9 DD5 DD10 DD4
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
I/O I/O O - O I - analog I I I I I/O I/O I/O - - I/O I/O I/O I/O
L/C L/C M - crystal pad crystal pad - current input Schmitt trigger C C Schmitt trigger AL/T AL/T AL/T - - AL/T AL/T AL/T AL/T
-
ground
crystal oscillator crystal oscillator output crystal oscillator/clock input - clock generator system test analog supply voltage VCO reference current power-on reset (active LOW) mode control input test pins
host host
ATAPI bus reset input from host (active LOW) data bus input/output
- - host
digital peripheral supply voltage 1 digital ground 6 data bus pin order of ATAPI interface matches the pinning of the 40-way IDE connector (slew rate limiting by control of drive capability into capacitive load of ATA bus)
1997 Aug 01
7
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL n.c. DD11 DD3 DD12 DD2 DD13 DD1 DD14 DD0 DD15 DMARQ/ DMACK DGND7 VDDD(pad2) DIOW DIOR IORDY DMACK/ DMARQ INTRQ DGND8 VDDD(pad3) IOCS16 DA1/DBWR PDIAG DA0 DA2/DBRD CS0/ SCSICS CS1 DASP INT2
PIN 71 to 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
TYPE - I/O I/O I/O I/O I/O I/O I/O I/O I/O O - - I I O I
DRIVE/ THRESHOLD - AL/T AL/T AL/T AL/T AL/T AL/T AL/T AL/T AL/T AL - - L/T L/T AH T A
GROUPING - host not connected
DESCRIPTION
data bus; pin order of ATAPI interface matches the pinning of the 40-way IDE connector (slew rate limiting by control of drive capability into capacitive load of ATA bus)
host - - host host host host host - - host host host host host host host host sub-CPU
DMA request/SCSI DMA acknowledge output (active LOW) digital ground 7 digital peripheral supply voltage 2 write cycle write enable/control register write input (active LOW) read cycle read enable/control register read input (active LOW) device is ready to transfer data output (active LOW) DMA acknowledge (active LOW)/SCSI DMA request input host interrupt request (NB 3-state output) digital ground 8 digital peripheral supply voltage 3 I/O port is 16-bit output (active LOW) address wire 1/DMA from generic interface is output from the SAA7391 (active LOW) ATAPI passed diagnostics input/output (active LOW) address wire 0 input/output address wire 2/DMA from generic interface is input to the SAA7391 (active LOW) chip select 1FX/generic interface chip select (active LOW) chip select 3FX input/output (active LOW) device active slave present input/output (active LOW) sub-CPU interrupt output from the SAA7391 drive block and UART
- - O I/O I/O I/O I/O I/O I/O I/O O
- - AH L/T AL/T L/T L/T L/T L/T AH/T L
1997 Aug 01
8
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL DGND9 VDDD(pad4) COMACK COMCLK n.c. COMOUT COMIN COMSYNC SYSSYNC SCCLK RD WR/R/W INT SRST SCA0/SCD0 SCA1/SCD1 DGND10 VDDD(pad5) SCA2/SCD2 SCA3/SCD3 SCA4/SCD4 SCA5/SCD5 SCA6/SCD6 SCA7/SCD7 DGND11 VDDD(core2) ALE PSEN SCA15 SCA14 SCA13 SCA12 DGND12 1997 Aug 01
PIN 103 104 105 106 107 to 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
TYPE - - I O - O I I I O I I O O I/O I/O - - I/O I/O I/O I/O I/O I/O - - I I I I I I -
DRIVE/ THRESHOLD - - C L - L C C C M T T L L L/T L/T - - L/T L/T L/T L/T L/T L/T - - T T T T T T -
GROUPING - - UART UART - UART UART UART UART sub-CPU sub-CPU sub-CPU sub-CPU sub-CPU sub-CPU - - sub-CPU
DESCRIPTION digital ground 9 digital peripheral supply voltage 4 command acknowledge/transmit flow control input serial data clock for synchronous mode output not connected transmit data output receive data input basic engine synchronization input basic engine synchronization input sub-CPU clock output sub-CPU read enable (active LOW) sub-CPU write enable/and read/write control input (active LOW) sub-CPU interrupt request output from host interface (active LOW) sub-CPU reset output multiplexed address/data lines
digital ground 10 digital peripheral supply voltage 6 multiplexed address/data lines
- - sub-CPU sub-CPU sub-CPU
digital ground 11 digital core supply voltage 2 demultiplex enable input for lower address lines program store enable (active LOW) upper address lines input
- 9
digital ground 12
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL SCA11 SCA10 SCA9 SCA8 n.c. n.c.
PIN 139 140 141 142 143 144
TYPE I I I I - -
DRIVE/ THRESHOLD T T T T - -
GROUPING sub-CPU
DESCRIPTION upper address lines input
- -
not connected not connected
1997 Aug 01
10
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
131 VDDD(core2)
129 SCA7/SCD7
128 SCA6/SCD6
127 SCA5/SCD5
126 SCA4/SCD4
125 SCA3/SCD3
121 SCA1/SCD1
120 SCA0/SCD0
113 COMSYNC
124 SCA2/SCD2
handbook, full pagewidth
138 DGND12 140 SCA10 139 SCA11 137 SCA12 136 SCA13 135 SCA14 134 SCA15 133 PSEN 142 SCA8 141 SCA9
123 VDDD(pad5)
114 SYSSYNC
111 COMOUT
130 DGND11
122 DGND10
117 WR/R/W
115 SCCLK
112 COMIN
119 SRST
132 ALE
144 n.c.
143 n.c.
110 n.c.
109 n.c. 108 n.c. 107 n.c. 106 COMCLK 105 COMACK 104 VDDD(pad4) 103 DGND9 102 INT2 101 DASP 100 CS1 99 CS0/SCICS 98 DA2/DBRD 97 DA0 96 PDIAG 95 DA1/DBWR 94 IOCS16 93 VDDD(pad3) 92 DGND8 91 INTRQ 90 DMACK/DMARQ 89 IORDY 88 DIOR 87 DIOW 86 VDDD(pad2) 85 DGND7 84 DMARQ/DMACK 83 DD15 82 DD0 81 DD14 80 DD1 79 DD13 78 DD2 77 DD12 76 DD3 75 DD11 74 n.c 73 n.c. n.c. 72
118 INT DD8 63
n.c. 1 n.c. 2 XDA0 3 XDA1 4 XDA2 5 VDDD(pad6) 6 DGND1 7 XDA3 8 XDA4 9 XDA5 10 XDA6 11 XDA7 12 XDA8 13 XDA9 14 XDA10 15 XDA11 16 DGND2 17 XRAS 18 XCAS 19 XWR 20 XDD0 21 XDD1 22 VDDD(core1) 23 DGND3 24 XDD2 25 XDD3 26 XDD4 27 XDD5 28 XDD6 29 XDD7 30 VDDD(pad7) 31 DGND4 32 SCKI1 33 WSI1 34 n.c. 35 n.c. 36
n.c. 37 n.c. 38 SDI1 39 SDO1 40 SFSY 41 RCK 42 SUBI 43 SUBO 44 CFLG 45 C2P0 46 DGND5 47 IECO 48 MCK 49 SCK2 50 WS2 51 SDO2 52 GND 53 CROUT 54 CRIN 55 VDDA 56 Iref 57 POR 58 TEST1 59 TEST2 60 RESET 61 DD7 62 DD6 64 VDDD(pad1) 65 DGND6 66 DD9 67 DD5 68 DD10 69 DD4 70 n.c. 71
SAA7391
116 RD
MGK542
Fig.2 Pin configuration.
1997 Aug 01
11
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
6.1 Detailed description of pin functions Q and R-W input/output subcode connections (4 pins) DESCRIPTION 3-wire subcode sync 3-wire subcode clock Q and R-W subcode input output subcode from encode COMMENT
SAA7391
Table 1
SYMBOL SFSY RCK SUBI SUBO
input subcode frame sync for receiving 3-wire subcode; output subcode frame sync for transmitting 3-wire subcode output bit clock for receiving 3-wire subcode; input bit clock for transmitting 3-wire subcode configurable for 3-wire or Philips V4 subcode mode; can use either RCK or WSI1 as clock references with appropriate dividers configurable for Philips SRI (Subcode Recordable Interface) 3-wire or Philips V4 subcode mode; can use either RCK, WSI1 or WS2 as clock references
Table 2
I2S-bus multimedia audio output (5 pins) DESCRIPTION 256fs or 384fs clock for multimedia master clock/IEC 958 clock or divided system clock for CD-DSP I2S-bus bit clock COMMENT Clock reference input pin when interface is in a master mode; a programmable divider is provided. This pin is also configurable as a programmable clock output intended as a clock reference for a CD-DSP. Should be pulled up if not in use. This is used for master and slave I2S-bus application as both modes are needed. For instance, the Philips multimedia CODEC is an I2S-bus slave, hence this must be a master interface. When driving some DACs, this interface can be a slave. word select strobe either master or slave I2S-bus multimedia data the IEC 958 output combines multimedia data and Q-W subcode
SYMBOL MCK
SCK2
WS2 SDO2 IECO Table 3
I2S-bus left/right strobe I2S-bus data to DAC/video decoder IEC 958 output
I2S-bus connections to CD engine (6 pins) DESCRIPTION I2S-bus bit clock COMMENT this is a separate clock to the multimedia bit clock as this rate is derived from the disc linear velocity
SYMBOL SCKI1 WSI1 SDI1 SDO1 C2P0 CFLG
I2S-bus left/right strobe I2S-bus data from CD-DSP I2S-bus data to CD-writer CD C2 error corrector flag from ERCO CD error corrector flags and absolute time sync these flags are used to indicate errors from second layer correction to the ERCO The absolute time sync is used in the CD input process for playing `Red Book' discs; the error corrector status is also read in from this signal, to provide an indication of C1 and C2 performance for CD-RW applications.
1997 Aug 01
12
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 4 ATAPI target mode interface ATAPI MEANING
SAA7391
ATAPI NAME RESET DD0 to DD7 DMARQ
ATAPI reset signal: the SAA7391 will not recognize a signal assertion shorter than 20 ns as a valid reset signal. ATAPI D0 to D7 DMA request: this signal, used for DMA data transfers between host and device, is asserted by the SAA7391 when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR and DIOW. DMA acknowledge: this signal is used by the host in response to DMARQ to initiate DMA transfers. This signal may be temporarily negated by the host to suspend the DMA transfer in process. ATAPI I/O port is a 16-bit open-drain output: during PIO transfer Modes 0, 1 or 2, IOCS16 indicates to the host system that the 16-bit data port has been addressed and that the device is prepared to send or receive a 16-bit data word. ATAPI I/O ready open-drain output: this signal is negated to extend the host transfer cycle of any host register access (read or write) when the SAA7391 is not ready to respond to a data transfer request. This signal is only enabled during DIOR/DIOW cycles to the SAA7391. When IORDY is not active, it is in the high-impedance (undriven) state. address bus (device address) ATAPI write strobe: the rising edge of DIOW latches data from the signals, DD0 to DD7 or DD0 to DD15 into a register or the data port of the SAA7391. The SAA7391 will not act on the data until it is latched. ATAPI read strobe: the falling edge of DIOR enables data from a register or data port of the SAA7391 onto the signals, DD0 to DD7 or DD0 to DD15. The rising edge of DIOR latches data at the host and the host will not act on the data until it is latched. ATAPI chip select 0 input: this is the chip select signal from the host used to select the ATA command block registers. This signal is also known as CS1FX. ATAPI chip select 1 input: this is the chip select signal from the host used to select the ATA control block registers. This signal is also known as CS3FX. ATAPI interrupt output: this signal is used to interrupt the host system. INTRQ is asserted only when the device has a pending interrupt, the device is selected, and the host has cleared the `nien' bit in the device control register. If the `nien' bit is equal to 1, or the device is not selected, this output is in a high-impedance state, regardless of the presence or absence of a pending interrupt. ATAPI passed diagnostics: this signal shall be asserted by device 1 to indicate to device 0 that it has completed diagnostics. ATAPI DASP (device active, device 1 present): this is a time-multiplexed signal which indicates that a device is active, or that device 1 is present. This signal is an open-drain output.
DD8 to DD15 ATAPI D8 to D15: these data bits are only used in accesses to the 16-bit data port
DMACK IOCS16
IORDY
DA0 to DA2 DIOW
DIOR
CS0 CS1 INTRQ
PDIAG DASP
1997 Aug 01
13
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 5 Generic host controller interface GENERIC INTERFACE NAME RESET D0 to D7 DMACK DMARQ DBWR DBRD SCSICS Miscellaneous pins SYMBOL CRIN CROUT Iref POR TEST1 and TEST2 Table 7 DESCRIPTION crystal oscillator/clock input crystal oscillator output VCO reference current power-on reset pin mode control test pins - - clock PLL multiplier - - COMMENT
SAA7391
ATAPI NAME RESET DD0 to DD7 DMARQ DMACK DA1 DA2 CS0 Table 6
GENERIC HOST CONTROLLER INTERFACE MEANING controller reset output controller DMA path/controller data and control bus (optional) controller upper DMA path (optional) DMA acknowledge to controller DMA request from controller DMA bus write to controller DMA bus read from controller controller chip select output for sub-CPU read/write cycles
DD8 to DD15 D8 to D15
Sub-CPU interface pins DESCRIPTION sub-CPU reset sub-CPU interrupt request output from host interface sub-CPU interrupt output from the SAA7391 drive block and UART sub-CPU clock out sub-CPU read enable sub-CPU write enable/ read/write control demultiplex enable input for lower address lines COMMENT active HIGH reset if XDD7 is pulled LOW during power-on reset; active LOW reset if XDD7 is pulled HIGH during power-on reset open-drain sub-processor interrupt from host interface open-drain sub-processor interrupt from drive and UART
SYMBOL SRST INT INT2
SCCLK RD WR/R/W ALE
- sub-CPU read enable strobe; if grounded permanently, the WR signal will act as read/write control input write enable; alternative usage is read/write if RD is held LOW at all times; WR has priority over RD at all times while HIGH, the lower address bits are latched from SCD0 to SCD7; should be used with a Schmitt trigger input to avoid false latching due to ground bounce on the 8051 microcontroller
1997 Aug 01
14
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL PSEN
DESCRIPTION program store enable
COMMENT if this pin is LOW then the 8051 microcontroller is accessing external program store; this pin is used as an active HIGH chip enable - -
SCD0 to SCD7/ SCA0 to SCA7 SCA8 to SCA15 Table 8
sub-CPU data bus multiplexed/low address bus sub-CPU address high bits
RAM interface pins DESCRIPTION RAM address bits, multiplexed for DRAM DRAM row address strobe DRAM column address strobe RAM write enable RAM data bus COMMENT up to 16 Mbytes DRAM only supported
SYMBOL XDA0 to XDA11 XRAS XCAS XWR XDD0 to XDD7 Table 9
Basic engine interface DESCRIPTION basic engine synchronization input basic engine synchronization input receive data transmit data serial data clock for synchronous mode command acknowledge/transmit flow control COMMENT generate interrupts on rising and/or falling edges generate interrupts on rising and/or falling edges - - - must be HIGH for synchronous mode to transmit next data byte into blocks. It then writes the blocks to the buffer memory and onboard ERCO RAM. Any detected errors are then corrected and over written into the buffer memory. Memory is segmented and addressable by segment pointers. The segment pointers consist of a block number, offset pointer and byte number within the block. The data within each segment is organised in the same manner (see Table 10). The arrangement of data within each segment in memory differs from other Philips devices, because of the different error correction processing possibilities within the SAA7391. Addresses 0 to 2355 are written to memory by the drive processor when enabled.
SYMBOL SYSSYNC COMSYNC COMIN COMOUT COMCLK COMACK
7
FUNCTIONAL DESCRIPTION
The SAA7391 device consists of a number of main functional units; a CD engine interface, a multimedia block, a microcontroller interface, an error detection and correction block, a host interface and a memory manager. There are also several smaller blocks including a clock control block and a UART for communication with the CD engine. Each block is independently controlled by a dedicated register set. These registers are memory mapped to the sub-CPU to allow for faster access. The external RAM can also be accessed directly from the microcontroller to support scratchpad accesses and thus eliminate the need for further memory devices in the system. 7.1 Memory field description
The CD input function of the SAA7391 buffer manager receives the main data stream in I2S-bus format from the CD-DSP, performs sync detection and partitions the data
1997 Aug 01
15
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 10 The memory map of a block in the buffer RAM for standard density mode (see Table 11) ADDRESS (OFFSET) 0 to 3 4 to 2339 2340 to 2351 2352 2353 2354 2355 2356 to 2451 2452 to 2463 2464 to 2465 2466 to 2559 header field block data field sync field copy of STAT0 copy of STAT1 copy of STAT2 number of C2 flags in sector (compressed format) 96-byte de-interleaved R-W data field 12-byte Q-subcode field copy of STAT4 field; only valid if ERCO did run on this block user work space TYPE OF DATA
SAA7391
Table 11 Description of Table 10 DATA Header field DESCRIPTION The 4-byte header data consists of a 3-byte block address of absolute time (minutes, seconds and frame, bytes 0 to 3). The fourth byte is for the mode of data: Mode 0 = zero mode Mode 1 = data storage with EDC and ECC Mode 2 = data storage Block data field in the CD-ROM mode the block data consists of 2048 bytes of user data and 288 bytes of auxiliary data User data: Mode 0= all 2048 bytes in user data are zero Mode 1= all 2048 bytes are available to the user Mode 2= all 2048 bytes are available to the user Auxiliary data: Mode 0= all 288 bytes in Aux data are zero Mode 1= the Aux field is in accordance with the EDC and ECC specification Mode 2= all 288 bytes are available to the user Sync field The 12-byte sync field is the next segment in memory. All bytes in the sync field are FFH, except the first and last bytes which are $00.
1997 Aug 01
16
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
DATA Number of C2 flags in sector (compressed format)
DESCRIPTION While storage of C2 flag positions is not possible as a consequence of the architecture of the SAA7391, a count of the number of flags seen per block is made in a single-byte counter. This counter packs the possibly 12-bit count into a single byte in the following way, at the expense of resolution in the count values for large counts. C2count_val = count (5 down to 0) x [4 ^ count (7 down to 6)], the resolution of the count is therefore: C2count_val 0 to 63: counter resolution = 1 C2count_val 64 to 255: counter resolution = 4 C2count_val 256 to 1023: counter resolution = 16 C2count_val 1024 to 4095: counter resolution = 64
96-byte de-interleaved R-W data field
Written to memory by the automatic Q-channel copy process (copy2 channel). If the copy process is not enabled, these fields are not written (see Section 7.3.5). These bytes may either be R-W de-interleaved or presented as raw Q-W subcode bytes. If the copy2 interleaving mode is set to raw, interleaved copying is still required as the subcode temporary holding buffer has Q bytes interspersed with the raw R-W. as above: these will not be separated out if the copy2 interleaving option is set to raw Address 2465 and 2466 are copies of the STAT4 register written by the ERCO when enabled. This allows the user to determine if the STAT4 register has been written to by the ERCO. If seg2465 = seg2466 then STAT4 definitely has not been written by the ERCO. If seg2465 seg2466 then STAT4 probably has not been written by the ERCO. Via direct access to buffer memory, the sub-CPU will be able to look at all of the blocks so far corrected, to check their status, in a background task. ERCO failures do not have to be dealt with immediately, as the status of every block loaded in to RAM is stored with that block, and it is not overwritten until the RAM block is filled with new data from CD input. The error corrector will be controlled additionally to permit the use of single pass P-Q or only EDC operation to allow for greater than n = 14 operation of the ERCO. The ERCO status will be copied into the RAM along with the data. This is possible because the RAM now has spare capacity to store the information, as part of the change from linear to segment/offset addressing. It is possible to program transfers into RAM of more than one block without processor intervention. It is also possible to continually loop on the same buffer area of RAM, by not altering the reload register values when the reload interrupt occurs.
12-byte Q-subcode field 2 copies of STAT4 field
7.1.1
DVD-ROM MEMORY FIELD INFORMATION
The buffer arrangement for DVD usage is basically the same (data followed by flags) but the size of the block data differs, and the ERCO flags are at a different offset, and as the ERCO is not in use, the flags relating to ERCO performance will not be valid.
1997 Aug 01
17
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.2 CD input control registers
SAA7391
The CD input process is intended to be as automated as possible. Data is read in from the front end, descrambled if in CD-ROM mode and then written to RAM. The registers that control the address of where the data is written to are in the memory processor block. The input data is synchronized, decoded and written to the buffer RAM. The input data format is software programmable. The synchronization is performed by using a sync detector and a sync interpolator. The sync detector can detect CD-ROM syncs and syncs from the CFLG pin, for use with Red Book, audio and for DVD. When no sync is found, it is optionally interpolated. After decoding, each full sector of data (2352 bytes) comprising sync, header and sub-header is written to the buffer RAM. The R-W and Q subcode is added by a software-initiated automatic block copy process. 7.2.1 REGISTERS ASSOCIATED WITH DATA IN PROCESS
Table 12 IFCONFIG (write only; address FF10H) (see Table 13) BIT 7 ipconfig BIT 6 ckdiv1 BIT 5 ckdiv0 BIT 4 subsel BIT 3 modulo 1 BIT 2 modulo 0 BIT 1 config swap BIT 0 config wclk
Table 13 Description of the IFCONFIG register bits BIT 7 6 and 5 NAME ipconfig ckdiv1 and ckdiv0 VALUE 0 1 00 01 10 11 4 3 and 2 subsel modulo 1 and modulo 0 0 1 00 01 10 11 1 0 config swap config wclk 0 1 0 1 modulo count 2064 modulo count 2064, but do not count bytes with flag = 1 the received data from the CD-DSP or drive FIFO is not swapped the received data from the CD-DSP or drive FIFO is swapped the internal `irclk' is not inverted the internal `irclk' is inverted I2S-bus mode EIAJ serial interface mode oversample, bit clock division ratio = 2 oversample, bit clock division ratio = 4 oversample, bit clock division ratio = 8 bit clock division ratio = 1 (no division) both copies of sub-header contribute to STAT1/sh0err to sh3err first copy only of sub-header contributes to STAT1/sh0err to sh3err modulo count 2352 MEANING
1997 Aug 01
18
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 14 CD input control registers (see Table 15) ADDRESS FF21H FF20H FF60H FF27H FF26H FF61H FF23H FF22H FF24H FF25H NAME DRIVECURSEG-L DRIVECURSEG-H DRIVECURCOUNT DRIVENEXTSEG-L DRIVENEXTSEG-H DRIVENEXTCOUNT DRIVEPREVSEG-L DRIVEPREVSEG-H DRIVEOFFSET-H DRIVEOFFSET-L BIT 7 s7 incen c7 s7 incen c7 s7 incen s7 s7 BIT 6 s6 wren c6 s6 wren c6 s6 wren s6 s6 BIT 5 s5 - c5 s5 - c5 s5 - s5 s5 BIT 4 s4 s12 c4 s4 s12 c4 s4 s12 s4 s4 BIT 3 s3 s11 c3 s3 s11 c3 s3 s11 s3 s3 BIT 2 s2 s10 c2 s2 s10 c2 s2 s10 s2 s2
SAA7391
BIT 1 s1 s9 c1 s1 s9 c1 s1 s9 s1 s1
BIT 0 s0 s8 c0 s0 s8 c0 s0 s8 s0 s0
There are two sets of address registers, one giving the current (DRIVECURSEG) number of the segment being filled and a segment/block counter. The other set contains the values (DRIVENEXTSEG) to use on completion of the current group of blocks being filled or emptied (in CD-R). The DRIVEPREVSEG register is loaded with the value of the DRIVECURSEG register at the end of each CD-ROM block. The reloading of the registers will trigger an interrupt, if enabled, of the sub-CPU, which will then have to reload the `next' registers. before the transfer requested in the `current' registers are exhausted. Memory is split into segments, each segment is 2560 bytes. The drive data is written one block at a time at the segment number pointed to by the DRIVECURSEG register. For the next block the `DRIVECURSEG' is updated as follows. Table 15 Description of the `incen' and `wren' bits (see Table 14) BIT 7 6 NAME incen(1) wren(2) VALUE 0 1 0 1 Notes 1. If `incen' is logic 1, the `DRIVECURSEG' pointer will increment every sector sync. The `DRIVECURCOUNT' will decrement every sector sync independent of `incen'. If `incen' is logic 0 then the pointer will remain fixed pointing at the same segment of RAM. If the reading of data from CD is enabled by the `wrreq' bit in the CTRL0 register, and the `wren' bit is logic 0 the segment will be repeatedly filled by the data coming in from the CD-ROM. 2. If `wren' is logic 1 and `incen' is logic 1 then the DRIVECURSEG register will increment with each sync time and the DRIVECURCOUNT register will decrement but data will not be written to external RAM. This allows the triggering of the reading of data or the writing of data some time in the future. Table 16 Control and status registers (see Tables 17, 18 and 19) ADDRESS FF0DH FF0EH FF0FH NAME CTRL0 CTRL1 CTRL2 BIT 7 decen syien modrq BIT 6 ahead syden formrq BIT 5 e01rq asyn - BIT 4 autoform cowren automode BIT 3 eramrq onepass mbckrq BIT 2 wrreq - - BIT 1 eccrq - dscren BIT 0 encode - - hold value of DRIVECURSEG increment DRIVECURSEG at the end of each CD-ROM block received enable writes of data transferred disable write of data transferred MEANING
1997 Aug 01
19
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 17 Description of the CTRL0 register bits (resetting the chip sets all the bits in this register to 0) BIT 7 NAME decen VALUE 0 1 6 5 ahead e01rq 0 1 0 1 4 3 2 autoform eramrq wrreq 0 1 0 1 0 1 1 0 eccrq encode 0 1 0 1 DESCRIPTION
SAA7391
disable decoding, drive in `full reset' state, no monitor of I2S-bus line, no interrupts enable decoding obsolete must be set to logic 1 disable error correction of bytes for which an error has been detected, but not yet corrected enable CRC miscorrection correction of the C2 flag bytes disable automatic Form detection enable automatic Form detection disable erasure flag use enable erasure flag use disable data writes to the buffer and pointer updates, only header and status information recovered enables data writes to the buffer and pointer updates disable ECC correction only EDC checking enable ECC correction, ERCO active read operation perform erasure correction on P and Q check symbols, resulting in encoder operation
Table 18 Description of the CTRL1 register bits (the reset function clears all the flags in this register) BIT 7 6 5 4 3 NAME syien syden asyn cowren onepass VALUE 0 1 0 1 0 1 0 1 0 1 disable sync interpolation enable sync interpolation disable sync detection enable sync detection CD-ROM sync detection audio sync detection disable rewriting of corrected error bytes enable rewriting of error bytes during error correction normal error corrector operation one pass only error correction DESCRIPTION
1997 Aug 01
20
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 19 Description of the CTRL2 register bits BIT 7 6 4 3 1 NAME modrq formrq automode mbckrq dscren VALUE 0 1 0 1 0 1 0 1 0 1 Mode 1 request Mode 2 request Form 1 request Form 2 request disable automatic determination of mode bit enable automatic determination of mode bit disable mode check function enable mode check function disable descrambling function enable descrambling function DESCRIPTION
SAA7391
Table 20 Sub-CPU registers during read (see Tables 21, 22, 23, 27 and 28) ADDRESS FF00H FF01H FF02H FF03H FF04H FF05H FF06H FF07H FF08H FF09H FF0AH FF0BH FF0CH NAME HEAD0 HEAD1 HEAD2 HEAD3 SUBHEAD0 SUBHEAD1 SUBHEAD2 SUBHEAD3 STAT0 STAT1 STAT2 STAT3 STAT4 - minerr rmod3 valst crcok ilsync secerr rmod2 - cblk nosyn blkerr rmod1 - uceblk BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
minutes seconds frames mode file number channel number submode coding Information lblk moderr rmod0 - - - sh0err mode - nocor sblk sh1err form - mode erablk sh2err rform1 - form - sh3err rform2 - qok
Table 21 Description of the STAT0 register bits (resetting the chip clears all bits in this register) BIT 7 6 5 4 3 NAME - ilsync nosyn lblk - VALUE - - 0 1 0 1 0 1 - - reserved reserved - sync pattern detected at word count 0 to 1174 - sync pattern inserted by sync interpolator not coincident with data sync - with `syien' at logic 0, no sync found; data block size has been extended reserved reserved DESCRIPTION
1997 Aug 01
21
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
BIT 2 1 0
NAME sblk erablk -
VALUE 0 1 0 1 - - - short block indication -
DESCRIPTION
one or more bytes of the block are flagged with C2 flags reserved reserved
Table 22 Description of the STAT1 register bits; address FF09H (see notes 1 and 2) BIT 7 minerr(3) Notes 1. Resetting the chip clears all bits in this register. 2. The bits in this register indicate the reliability of data in the HEAD0 to HEAD3 and SUBHEAD0 to SUBHEAD3 registers. 3. Bits `minerr', `secerr', `blkerr' and `moderr' indicate errors in the minutes, seconds, frames and mode bytes in the header of the current block. 4. Bits `sh0err' to `sh3err' indicate errors in the respective bytes in the subheader. Table 23 Description of the STAT2 register bits; address FF0AH (see Tables 24, 25 and 26) BIT 7 rmod3 BIT 6 rmod2 BIT 5 rmod1 BIT 4 rmod0 BIT 3 mode BIT 2 form BIT 1 rform1 BIT 0 rform2 BIT 6 secerr(3) BIT 5 blkerr(3) BIT 4 moderr(3) BIT 3 sh0err(4) BIT 2 sh1err(4) BIT 1 sh2err(4) BIT 0 sh3err(4)
Table 24 Description of the `mode' and `form' bits mode 0 1 X form 0 0 1 Mode 1 Mode 2, Form 1 Mode 2, Form 2 or ECC correction impossible SETTING
Table 25 Description of the `rform' bits rform1 0 0 1 rform2 0 1 X Form 1 Form 2 error in Form byte MEANING
1997 Aug 01
22
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 26 Description of the `rmod' bits rmod3 to rmod30(1) 0000 0001 0010 0011 0100 0101 0110 0111 1XXX 1111 Note MEANING mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 packet written CD-R, run in/run out, link, XXX is mode mode = 7 or error in mode byte
SAA7391
1. rmod3 = bit 7 #, bit 6 #, bit 5 #, bit 4 #, bit 3 # of C2P0 (where # is logic OR). This is non-zero for packet written CD-R. rmod2 = bit 2 # CFLG. rmod1 = bit 1 # CFLG. rmod0 = bit 0 # CFLG. Table 27 Description of the STAT3 register bit BIT 7 NAME valst VALUE 0 1 registers invalid DESCRIPTION registers associated with decoder interrupt valid
Table 28 Description of the STAT4 register bits (this register contains the interrupt status on reading) BIT 7 6 5 4 3 2 1 0 NAME crcok cblk uceblk - nocor mode form qok VALUE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - cyclic redundancy check OK - there has been an error in this block - uncorrectable errors in block reserved reserved - ERCO was not started on this block Mode 1 used in correcting this block Mode 2 used in correcting this block Form 1 used in correcting this block Form 2 used in correcting this block Q channel CRC no error Q channel CRC error DESCRIPTION
1997 Aug 01
23
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 29 Auxiliary segment pointer ADDRESS FF29H FF28H NAME AUXSEGMENT-L AUXSEGMENT-H BIT 7 s7 - BIT 6 s6 - BIT 5 s5 - BIT 4 s4 s12 BIT 3 s3 s11 BIT 2 s2 s10
SAA7391
BIT 1 s1 s9
BIT 0 s0 s8
The auxiliary segment pointer points at a group of segments which hold the data FIFOs used in the SAA7391. These are the `large' FIFOs rather than the small resynchronizing FIFOs inside the SAA7391. The subcode input/output and n = 1 I2S-bus interfaces use these FIFOs (in addition, the shadow debug registers can use some of this space). The FIFOs are arranged to optimally occupy a contiguous group of segments in the external RAM. 7.3 Multimedia output interface
* Permits CAV and quasi-CLV systems to maintain n = 1 audio output * Basic channel swap, mono-L or mono-R modes, includes muting and L + R summed mono * IEC 958 output with subcode Q-W for use in CAV and other modes where there is no n = 1 clock in the CD-DSP subsystem - IEC 958 interface has fully programmable category code and copyright bits for flexibility - Subcode on IEC 958 is only available in CD-ROM mode, because the subcode output FIFO is shared. * Master and slave I2S-bus modes are available - IEC 958 is only available when the I2S-bus is in the master mode. * Can be configured to provide a clock for an external CD-DSP function via the MCK pin * Can operate in 64fs or 48fs I2S-bus modes * IEC 958 can operate at n = 2 although not permitted by standard. 7.3.1 SUBCODE INPUT BLOCK
This block deals with subcode input and output in addition to an audio output which is independent of the I2S-bus input output path connected to the CD-R engine. Q and R-W subcode features: * Supports semiautomatic de-interleaving/interleaving * Subcode sync is aligned with the start of the current block in RAM * Supports subcode resynchronization when subcode sync is lost * Supports Philips `V4' and 3-wire formats (only one RCK and one SFSY pin shared with subcode output) * Has selectable polarity on RCK * Uses WSI1 pin as timing reference * Can insert `P' bit in 3-wire mode via sub-CPU accessible register bit * Supports regeneration of subcode from IEC 958 output using WS2 as timing reference * Can accept subcode input while I2S-bus from CD-DSP is oversampled audio at n = 2 or n = 4 oversample * Subcode for CD-recordable applications is supported in Philips V4 or 3-wire Philips Subcode Recordable Interface (SRI). This SRI mode is only compatible with CDR60. Audio output (multimedia) features: * Has data output for simple audio or digital video for n = 1 or n = 2 rate regardless of input CD-DSP data rate * 4096-byte FIFO for audio samples, requires firmware polling for refills using the block copy engine
7.3.1.1
Q-W subcode handling
The subcode data is initially converted from serial-to-parallel format and is then handled as Q-W bytes. The de-interleaving is performed by a de-interleaving block copy mode in the memory processor's block copy engine. Subcode blocks will always be aligned with a block of CD-ROM data, although the subcode Minutes, Seconds, Frames (MSF) absolute time may have an uncertainty of 5 frames in terms of the actual CD-ROM block it is referring to. This offset is unknown but consistent in any given application. The block copy engine will be automatically triggered when the subcode synchronization is found. The error corrector will then compute the CRC syndrome of the subcode and deposit it in the CRC bytes. The sub-CPU will have to perform the actual correction if a non-zero syndrome appears. This syndrome, if calculated during encoding by the ERCO, can be used as the CRC written to disc for the subcode. 24
1997 Aug 01
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.3.1.2 Description of subcode interface
SAA7391
The subcode interface allows the reception and transmission of subcodes. The subcodes will be received/transmitted to two on-chip 512-byte FIFOs, one for transmit and one for receive. No interrupts are associated with these FIFOs as the block copy engine removes data or fills these as necessary. There is, however, an interrupt which is asserted when a sync is found in an unexpected location. 7.3.2 SUBCODE MODE TRANSMIT CONTROL REGISTER
Table 30 Subcode mode transmit control register (SUBMODETX; address FF13H); see Table 31 BIT 7 - BIT 6 - BIT 5 - BIT 4 pbit BIT 3 - BIT 2 txena BIT 1 - BIT 0 V4
Table 31 Description of the SUBMODETX register bits BIT 4 2 0 NAME pbit txena V4 VALUE 0 1 0 1 0 1 Note 1. Philips V4 subcode transmit mode must be selected for correct insertion of subcode into the IEC 958 data stream. For CD-recordable applications with CDR60 the Philips SRI subcode mode allows for correct subcode frame synchronization between the SAA7391 and the CDR60 device before recording commences. Table 32 Subcode mode receive control register (SUBMODERX, address FF17H); see Table 33 BIT 7 - BIT 6 - BIT 5 - BIT 4 wsdiv1 BIT 3 wsdiv0 BIT 2 rxena BIT 1 rckinvrx BIT 0 rxsubqw P bit logic 0 in 3-wire mode subcode transmit interface is disabled subcode transmit interface is enabled Philips SRI 3-wire subcode Philips V4 mode; note 1 DESCRIPTION P bit logic 1 in 3-wire mode (default)
Table 33 Description of the SUBMODERX register bits BIT 4 3 2 1 0 NAME wsdiv1 wsdiv0 rxena rckinvrx rxsubqw VALUE 00 01 10 11 0 1 0 1 0 1 2 times oversampling 4 times oversampling 8 times oversampling subcode receive interface is disabled subcode receive interface is enabled normal RCK output invert the RCK output 3-wire subcode Philips V4 mode (sub Q-W) DESCRIPTION no oversampling (normal CD-ROM modes)
1997 Aug 01
25
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 34 Subcode general (input/output pointers) ADDRESS FF2BH FF2AH FF2FH FF2EH FF2DH FF2CH FF31H FF30H NAME SUBPOINTR-L SUBPOINTR-H SUBPOINTW-L SUBPOINTW-H SUBBASEPOINTR-L SUBBASEPOINTR-H SUBBASEPOINTW-L SUBBASEPOINTW-H BIT 7 s7 - s7 - s7 - s7 - BIT 6 s6 - s6 - s6 - s6 - BIT 5 s5 - s5 - s5 - s5 - BIT 4 s4 - s4 - s4 - s4 - BIT 3 s3 - s3 - s3 - s3 - BIT 2 s2 - s2 - s2 - s2 -
SAA7391
BIT 1 s1 - s1 - s1 - s1 -
BIT 0 s0 s8 s0 s8 s0 s8 s0 s8
7.3.2.1
Subcode buffering
The subcode is buffered in the AUXSEGMENT register. Two offset pointers, SUBPOINTR-L and SUBPOINTR-H, and SUBPOINTW-L and SUBPOINTW-H are associated with it. The R pointer is for the subcode output and the W pointer for the subcode input. Pointers are also provided to point at the offset into the AUXSEGMENT register where the start of a subcode frame will be found, SUBBASEPOINTR-L and SUBBASEPOINTR-H and SUBBASEPOINTW-L and SUBBASEPOINTW-H. The block copy engine is expected to use these to automatically move the subcode into the segment pointed at by DRIVECURSEG register. 7.3.3 GENERAL DESCRIPTION OF THE MULTIMEDIA OUTPUT INTERFACE
Table 35 Multimedia output interface register bits ADDRESS FF32H FF33H FF34H FF35H FF16H FF70H FF71H FF14H FF15H Notes 1. See Table 36. 2. See Table 39. 3. See Table 38. 4. See Table 41. NAME CDDA-H CDDA-L DAOFFSET-H DAOFFSET-L MMCTRL(1) IECCTRL(2) IECCAT MMAUD(3) MCK_CON(4) iecen cat7 daen - data cat6 eiaj - BIT 7 - a7 - a7 BIT 6 - a6 - a6 mmdiv copyright cat5 master - preem cat4 - - BIT 5 - a5 - a5 BIT 4 - a4 - a4 BIT 3 - a3 a11 a3 spdx2 vbit cat3 mckxtal leftmode mckoe BIT 2 - a2 a10 a2 wslen - cat2 cat1 div BIT 1 a9 a1 a9 a1 accu cat0 rightmode BIT 0 a8 a0 a8 a0
mcksel
1997 Aug 01
26
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.3.3.1 Basic description of the multimedia output interface
SAA7391
The multimedia data output may be used either with an internal clock or an externally provided clock. The clock used should be a correct multiple of 44100 Hz in order for the block to correctly output IEC 958. The multimedia interface data FIFO is located in the block of segments associated with AUXSEGMENT master/slave mode operation (see Fig.3).
handbook, full pagewidth
e.g. DAC SCK WS SDO2
SAA7391
e.g. DAC SCK WS SDO2
SAA7391
slave: master = 0
master: master = 1
MGK513
Fig.3 Master/slave mode operation.
Table 36 Description of the MMCTRL register bits BIT 7 6 5 4 3 2 1 and 0 spdx2 wslen mcksel NAME mmdiv VALUE - - - - 0 1 0 1 00 01 10 I2S-bus output is single speed I2S-bus (and IEC 958) output is double speed; video applications I2S-bus bit clock is 64 times the sample rate I2S-bus bit clock is 48 times the sample rate multimedia internal clock is CRIN pin multimedia internal clock is MCK pin multimedia internal clock is system clock see Table 37 DESCRIPTION
1997 Aug 01
27
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 37 mmdiv/mcksel relationship to clocks needed for I2S-bus and IEC 958 I2S-BUS OUTPUT mcksel DIVIDER CODE mmdiv MULTIMEDIA CLOCK OVERSAMPLE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Notes 48fs 64fs 96fs 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 1536fs FREQUENCY (Hz) 2116800 2822400 4233600 5644800 8467200 11289600 16934400 22579200 33868800 45158400 67737600 I2S-BUS, 48 BITS PER SAMPLE n=1 1(1) - 2 - 4 - 8 - 16 - 32 n=2 - - 1(1) - 2 - 4 - 8 - 16 I2S-BUS, 64 BITS PER SAMPLE n=1 - 1(1) 1.5(1) 2 3 4 6 8 12 16 24 n=2 - - - 1(1) 1.5(1) 2 3 4 6 8 12
SAA7391
IEC 958
n=1 - - - 1 1.5 2 3 4 6 8 12
(n = 2) - - - - - (1) (1.5)(2) (2) (3) (4) (6)
1. For these combinations the duty factor of the output SCK2 clock is not necessarily 50%. These combinations are therefore not recommended. 2. This is illegal but possible. Table 38 Description of the MMAUD register control bits BIT 7 6 5 3 2 1 rightmode NAME daen(1) eiaj master leftmode VALUE 0 1 0 1 0 1 00 01 10 11 00 01 10 11 DESCRIPTION CD-DA interface is off CD-DA Interface is on I2S-bus serial mode EIAJ16 serial mode I2S-bus is slave I2S-bus is master I2S-bus left channel output is left (default) I2S-bus left channel output is right I2S-bus left channel output is muted reserved I2S-bus right channel output is right (default). This is the opposite default to left channel. I2S-bus right channel output is left I2S-bus right channel output is muted reserved
0
Note 1. If enabled, data is written to the CDDA interface from a FIFO located in the CDDA register space. If either `daen' = 1 or `iecen' = 1 (ieccrtl), the interface will become active. 1997 Aug 01 28
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.3.4 IEC 958/EBU OUTPUT
SAA7391
Table 39 Description of the IECCTRL register control bits (notes 1 and 2) BIT 7 6 5 4 NAME iecen data copyright preem VALUE 0 1 0 1 0 1 0 1 3 vbit 0 1 2 1 to 0 - accu - - 00 01 10 11 Notes 1. In order for the IEC interface to operate correctly, it will require a clock at 128fs to be present. 2. The `vbit' is copied into the V bit of the IEC 958 frame. Table 40 IEC 958 system channel bit mapping (note 1) BIT OFFSET BIT NUMBER +0 0 8 16 24 Note 1. The C bit is updated on an IEC frame-by-frame basis, the bit offset corresponds to the IEC frame offset. They are repeated for both left and right channels. Bit 0 is present in the C bit of the first sample pair of the IEC superframe of 192 sample pairs. 0 cat0 0 0 +1 data cat1 0 0 +2 copyright cat2 0 0 +3 preem cat3 0 0 +4 - cat4 0 accu0 +5 0 cat5 0 accu1 +6 0 cat6 0 0 +7 0 cat7 0 0 IEC 958 interface is off IEC 958 Interface is on IEC 958 contains audio information IEC 958 contains data IEC 958 C bit in system channel is logic 0 IEC 958 C bit in system channel is logic 1 audio pre-emphasis off/IEC 958 contains data audio pre-emphasis on (only appears in IEC 958 C channel; de-emphasis bit is not implemented in the SAA7391) audio samples suitable for conversion mute audio, or signal is data and should not be digital-to-analog converted at any time reserved reserved level II clock accuracy level III clock accuracy (depends on mck/system clock) reserved reserved DESCRIPTION
1997 Aug 01
29
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 41 Description of the MCK_CON register bits (note 1) BIT 3 2 1 and 0 NAME mckxtal mckoe div VALUE 0 1 0 1 00 01 10 11 Note MCK reference is the CRIN pin MCK pin is 3-state, an input to the MM block (default) MCK pin is output MCK reference is divided by 2 (default) MCK reference is divided by 1.5 MCK reference is divided by 1 MCK reference is divided by 4 DESCRIPTION MCK reference is system clock (default)
SAA7391
1. The bits in this register control the use of the MCK pin as an output to clock a CD-DSP. The division ratios chosen are suitable for the SAA7335 or CDR60 devices. If the MCK pin is not being used then it should be pulled HIGH for correct selection of the internal multimedia clocks. 7.3.5 MEMORY-TO-MEMORY BLOCK COPY FUNCTION The only register that is user programmable in the subcode copying engine is the COPYFROM2OFFSET pointer. The `COPYFROM2OFFSET' pointer is set up by the sub-CPU to point into the subcode input FIFO. It points at the first byte of subcode to be copied into the current host data block. Once triggered, this copy is automatically set-up to correctly transfer the next block of subcode correctly without host intervention. Copying of the subcode in the opposite direction is performed by the sub-CPU commanding an interleaved copy of data using the user block copy registers. This does not have to be as fast as the recorder function is only specified to n 8. Hence it is not automated.
This function is provided for the user to move and copy blocks of RAM. Two pointer sets are provided. The second of these is for the semi-automatic subcode copying function of the subcode in the block. It is independent of the first copy register set, which is available for e.g. audio copying needed in the PLAY AUDIO function with the SAA7391, and for subcode copying when recording. When started, the copy process will copy the COPYCOUNT register bytes from the `FROM' pointers to the `TO' pointers. A copying process may be stopped during its operation by writing to the `copyend' bit.
7.3.5.1
Automatic copying of received subcode-to-data block
When enabled, the newly received subcode will be automatically transferred to the current host segment in RAM.
1997 Aug 01
30
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 42 Block copy registers ADDRESS FF67H FF3BH FF3AH FF37H FF36H FF3DH FF3CH FF39H FF38H FF63H FF62H FF3FH FF3EH FF41H FF40H Note 1. See Table 43. Table 43 Description of the COPYCONTROL register bits BIT 7 6 5 4 3 2 1 0 NAME dfrom dto dfrom2 dto2 en1 en2 raw sub_deint_order VALUE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DESCRIPTION linear addressing with COPYOFFSET interleaved addressing with COPYOFFSET linear addressing with COPYTOOFFSET interleaved addressing with COPYTOOFFSET NAME COPYCONTROL(1) COPYFROMSEG-L COPYFROMSEG-H COPYFROMOFFSET-L COPYFROMOFFSET-H COPYTOSEG-L COPYTOSEG-H COPYTOOFFSET-L COPYTOOFFSET-H COPYCOUNT-L COPYCOUNT-H FROM2OFFSET-L FROM2OFFSET-H TO2OFFSET-L TO2OFFSET-H BIT 7 dfrom s7 - a7 - s7 - a7 - c7 - a7 - a7 - BIT 6 dto s6 - a6 - s6 - a6 - c6 - a6 - a6 - BIT 5 dfrom2 s5 - a5 - s5 - a5 - c5 - a5 - a5 - BIT 4 dto2 s4 - a4 - s4 - a4 - c4 - a4 - a4 - BIT 3 en1 s3 s11 a3 a11 s3 s11 a3 a11 c3 c11 a3 a11 a3 a11 BIT 2 en2 s2 s10 a2 a10 s2 s10 a2 a10 c2 c10 a2 a10 a2 a10 BIT 1 raw s1 s9 a1 a9 s1 s9 a1 a9 c1 c9 a1 a9 a1 a9
SAA7391
BIT 0 sub_deint_order s0 s8 a0 a8 s0 s8 a0 a8 c0 c8 a0 a8 a0 -
linear addressing in copy from block, subcode copy engine interleaved addressing in copy to block, subcode copy engine linear addressing in copy to block, subcode copy engine interleaved addressing in copy to block, user block copy engine user block copy disabled user block copy enabled subcode block copy disabled subcode block copy enabled enable complete subcode de-interleaving process de-interleave R-W bytes, but skip Q byte de-interleaving de-interleave received subcode (CD-ROM) Interleave transmitted subcode (CD-R)
1997 Aug 01
31
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.4 Interrupt registers
SAA7391
The interrupt system in the SAA7391 is intended to make it possible to acknowledge interrupts both independently without interference or together. There are two interrupt pins to the sub-CPU from the SAA7391. The INT pin is associated only with the host interface register IFSTAT (address FF92H). The INT2 pin is associated with 6 interrupt registers which cover the SAA7391 drive block and UART. Two status/reset registers and two interrupt enable register for the drive block and one status/reset register plus an interrupt enable register for the UART. Table 44 IFSTAT interrupt register for the host interface; address FF92H (note 1) ACCESS R Note 1. Interrupt status bits are described in the host interface; see Section 7.5.3.18. 7.4.1 INTERRUPT 1 BIT 7 cmdi BIT 6 dtei BIT 5 drqi BIT 4 ultra_stop BIT 3 dtbsy BIT 2 srsti BIT 1 reset08 BIT 0 a0comp/ crc_error
By writing a logic 1 to the INT1RESET register the bits will negate the INT1STATUS register bits. Writing a logic 1 to an INT1ENABLE bit will enable the corresponding status bit. Writing a logic 0 will disable the status to zero. Table 45 INT1STATUS: drive interrupt register status; address FF7AH (see Table 54) ACCESS R BIT 7 dec BIT 6 nocor BIT 5 erablk BIT 4 cblk BIT 3 uceblk BIT 2 crc-ng BIT 1 q-ng BIT 0 int2
Table 46 INT1RESET: drive interrupt register reset; address FF7AH (see Table 54) ACCESS W BIT 7 dec BIT 6 nocor BIT 5 erablk BIT 4 cblk BIT 3 uceblk BIT 2 crc-ng BIT 1 q-ng BIT 0 -
7.4.1.1
INT1ENABLE: drive interrupt register enable bits
Table 47 INT1ENABLE: drive interrupt register enable; address FF7BH (see Table 54) ACCESS W BIT 7 dec BIT 6 nocor BIT 5 erablk BIT 4 cblk BIT 3 uceblk BIT 2 crc-ng BIT 1 q-ng BIT 0 int2
1997 Aug 01
32
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.4.2 INTERRUPT 2
SAA7391
By writing a logic 1 to INT2RESET register bits will negate the INT2STATUS bit. Writing a logic 1 to an INT2ENABLE bit will enable the corresponding status bit. Writing a logic 0 will disable the status to zero. Table 48 INT2STATUS: drive interrupt register status; address FF7CH (see Table 54) ACCESS R BIT 7 hostbyte countzero BIT 6 drive reload BIT 5 hostrel countzero BIT 4 copyend BIT 3 subcode syncint BIT 2 dmatxint BIT 1 int1 BIT 0 uartint
Table 49 INT2RESET: drive interrupt register reset; address FF7CH (see Table 54) ACCESS W BIT 7 hostbyte countzero BIT 6 drive reload BIT 5 hostrel countzero BIT 4 copyend BIT 3 subcode syncint BIT 2 dmatxini BIT 1 - BIT 0 -
Table 50 INT2ENABLE: drive interrupt register enable; address FF7DH (see Table 54) ACCESS W BIT 7 hostbyte countzero UART INTERRUPT BIT 6 drive reload BIT 5 hostrel countzero BIT 4 copyend BIT 3 subcode syncint BIT 2 dmatxini BIT 1 - BIT 0 -
7.4.3
By writing a logic 1 to the INT2RESET register bits will negate the INT2STATUS bit. Writing a logic 1 to an INT2ENABLE bit will enable the corresponding status bit. Writing a logic 0 will disable the status to zero. The INT2 interrupt corresponds to not (INT1 or INT2 or UARTINT). Table 51 UARTINTSTATUS: UART interrupt register status; address FF78H (see Table 54) ACCESS R BIT 7 comsync BIT 6 syssync BIT 5 notcomsync BIT 4 notsyssync BIT 3 nottxbfull BIT 2 rxbfull BIT 1 overrun BIT 0 rxparity
Table 52 UARTINTRESET: UART interrupt register reset; address FF78H (see Table 54) ACCESS W BIT 7 comsync BIT 6 syssync BIT 5 notcomsync BIT 4 notsyssync BIT 3 nottxbfull BIT 2 rxbfull BIT 1 overrun BIT 0 rxparity
Table 53 UARTINTENABLE: UART interrupt register enable; address FF79H (see Table 54) ACCESS W BIT 7 comsync BIT 6 syssync BIT 5 notcomsync BIT 4 notsyssync BIT 3 nottxbfull BIT 2 rxbfull BIT 1 overrun BIT 0 rxparity
1997 Aug 01
33
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 54 Description of the interrupt register bits REGISTER INTERRUPT block by block decoder interrupt ERCO cannot be started on current block nocor erablk cblk uceblk crc-ng q-ng int2 DESCRIPTION
SAA7391
INTERRUPT 1 dec
one or more bytes coming from CD-DSP have been flagged with error corrected current block. one or more bytes remain in error bad CRC on current block bad Q CRC on current block indicates that interrupt is caused by an enabled interrupt from INT2
INTERRUPT 2 hostbytecountzero the host counter decremented to zero and may have been reloaded; requires sub-CPU intervention when reload is disabled drivereload copyend subcode syncint dmatxint int1 uartint UART INT comsync syssync notcomsync notsyssync nottxbfull rxbfull overrun rxparity 7.5 7.5.1 Host interface INTRODUCTION drive processing pointers have reloaded copy process has finished subcode receive block detection of early subcode 98 frame sync period asserts when `dmacount' reaches zero with `dmaon' bit set indicates that interrupt is caused by an enabled interrupt from INT1 indicates that the interrupt is from the UART interrupt register UART COMSYNC pin rising edge interrupt SYSSYNC pin rising edge interrupt COMSYNC falling edge interrupt SYSSYNC pin falling edge interrupt transmit buffer has become empty receive buffer has become full receive buffer has overrun a character has been received with illegal parity * Supports ATA Packet Interface (ATAPI revision 2.6) for CD-ROMs * Supports ATA/ATAPI 16-bit PIO data transfers for Modes 0, 1, 2, 3 and 4 * Supports ATA/ATAPI single/multi word DMA transfers for Modes 0, 1 and 2 * Supports ultra DMA for Mode 0 * Supports generic interface connection to external SCSI controller device (NCR 53CF92) * Command and status registers of external generic interface controller are optionally mapped via the host interface pins of the SAA7391. the SAA7391 becomes the bus master. * Operates automatically with multi-block host data transfers hostcursegcntzero the host reload count decremented to zero; no more host reloads are available
The SAA7391 host interface block is responsible for the transfer of data and control information between the memory processor, external host and microcontroller. The host interface operates in conjunction with the SAA7391 Auxiliary block (Aux block). The Aux block contains several registers that automate the SAA7391 memory processor in its task of supplying the host interface with data from the buffer memory and receiving data from the host interface to be placed in the buffer memory. The host interface automates data transfer to and from the host, whereas the Aux block automates data transfer, via the memory processor and buffer memory, depending on the CD format. The host interface features are as follows: 1997 Aug 01 34
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
* Reduces microcontroller load in simple streaming transfers to or from host using a circular buffer * Recognizes ATA SRST, the ATAPI reset command (0X08) and the ATAPI packet command (0XA0) and handles these automatically in ATAPI mode * Handles unexpected ATA commands during PIO data transfers * Provides automatic DRQ for all PIO data transfers * Provides automatic detection of ATAPI packet (A0) command and reception of the packet bytes * Provides automatic completion sequence for PIO DMA and ultra DMA transfers * Supports shadowing of registers for single drive configurations with non-existent slave. 7.5.2 DESCRIPTION OF THE HOST INTERFACE BLOCK
SAA7391
The host interface has a shadow status register to permit proper ATA operation. The PDIAG and DASP signals are controlled by the register bits in the host interface block. The microcontroller has access to all registers in the host interface block. The microcontroller can control all operations required for data transfer to and from the host, but may configure the host interface sequencer to automate the following three operations: 1. Automation of detection of the A0 packet command and reception of the 12-byte packet. 2. Automation of the data transfer sequences for PIO, DMA and ultra DMA modes of data transfer. 3. Automation of completion sequences for PIO, DMA and ultra DMA modes of data transfer. The host interface provides a generic interface mode for a glueless connection to an external SCSI controller device. In this mode the microcontroller can configure the registers of the SCSI controller device and initiate DMA transfers.
The host interface block consists of three FIFOs which can be configured by the DTCTR register to generate the required data path through the host interface block. The design supports ATAPI (revision 2.6) for CD-ROM interfaces.
7.5.2.1
The SAA7391 host interface ATAPI registers visible to the host
Table 55 Host interface registers as seen from the host (note 1) CS0 1 1 0 0 0 0 0 0 0 0 0 0 Note 1. The operation of these registers complies with the ATA-3 specification (revision 6) and the ATAPI specification (revision 2.6). CS1 0 0 1 1 1 1 1 1 1 1 1 1 DA2 1 1 0 0 0 0 0 1 1 1 1 1 DA1 1 1 0 0 0 1 1 0 0 1 1 1 DA0 0 1 0 1 1 0 1 0 1 0 1 1 HOST READ (DIOR) ALT STATUS: alternative status ADRADR: ATAPI drive address DATA: data register AERR: ATAPI error register SHERR: ATAPI error register (shadow) AINTR: ATAPI interrupt reason register ASAMT: ATAPI SAM TAG register DBCL: ATAPI byte count low DBCH: ATAPI byte count high ADRSEL: ATAPI drive select register ASTAT: ATAPI status register SHSTAT: ATAPI status register (shadow) HOST WRITE (DIOW) ADCTRL: ATAPI device control not used DATA: data register AFEAT: ATAPI features register unused unused ASAMT: ATAPI SAM TAG register DBCL: ATAPI byte count low DBCH: ATAPI byte count high ADRSEL: ATAPI drive select register ACMD: ATAPI command register unused
1997 Aug 01
35
7.5.2.2
The SAA7391 host interface registers visible by the microcontroller
1997 Aug 01 36
Philips Semiconductors
ATAPI CD-R block encoder/decoder
The registers listed in Table 56 are used by the microcontroller to control the operation of the host interface block. The ATAPI command block registers (ADATA, ASTAT, ADRADR, ASAMT, ADRSEL, AINTR, AERR, ACMD, ADCTR, AFEAT and APCMD) are dual port registers which can be accessed either by the microcontroller or the host PC depending the state of the BSY flag, bit 7 of the ASTAT register. Table 56 Host registers as seen by the microcontroller ADDR FF80H FF81H FF82H FF83H FF84H FF85H FF86H FF87H FF88H FF89H FF8AH FF8BH FF8CH FF8DH FF8EH FF8FH FF90H FF91H FF92H FF93H FF94H FF95H FF96H FF97H ACCESS W RW RW RW W W W RW W W RW RW RW RW RW R R R RW R RW RW RW RW NAME ADATA IFCTRL DBCL DBCH DTRG DTACK RESET ASTAT ITRG ADRADR ASAMT DTCTR ADRSEL AINTR AERR ACMD ADCTR AFEAT IFSTAT APCMD HICONF0 HICONF1 HISEQ SHSTAT ultractrl2 to ultractrl0 dmaen autoa0 0 shhpbit autodrq 0 udmaoff comp 0 cmdi dtei drqi reserved dmamode dma reserved ATAPI Status register (see Table 61) host Interrupt Trigger register ATAPI Drive Address register ATAPI SAM tag register ultra_dma rdrv trant ATAPI Drive Select register ATAPI Interrupt Reason register ATAPI Error Register ATAPI Command register ATAPI Device Control Register ATAPI Features register ultra_stop dtbsy srsti reset08 a0comp/ crc_error cmdien dteien drqien BIT 7 BIT 6 BIT 5 BIT 4 ultra_ stopien BIT 3 - BIT 2 srstien BIT 1 - - BIT 0
ATAPI Data register
Data Byte Count register (bits 7 to 0) Data Byte Count register (bits 15 to 8) Data transfer Trigger register Data Transfer Acknowledge register hsel
Objective specification
ATAPI Packet Command register dynhosthiprior flushfifo error 0 - sus_seq 0 hrequest unmaskdtie repeat autoA0 0 clear_reg - 0 shadow ultractrl3 - shcheck
SAA7391
1997 Aug 01 37
Philips Semiconductors
ADDR FF98H FF99H FF9AH FFA0H FFA1H FFA2H FFA3H FFA4H FFA5H FFA6H
ACCESS RW RW R RW RW RW RW RW RW R
NAME SHERR HIDEV HISTAT TRANSFER COUNTER TRANSFER COUNTER TRANSFER COUNTER TRANSFER COUNTER PACKETSIZE STORE PACKETSIZE STORE SEQUENCER _STATUS
BIT 7 0 pdiag out
BIT 6 0 pdiag pad enable
BIT 5 0 dasp out
BIT 4 0 dasp pad enable
BIT 3 0 pdiag in
BIT 2 shabrt dasp in
BIT 1 0 -
BIT 0 0 hosthipi
ATAPI CD-R block encoder/decoder
not used byte count (bits 7 to 0) byte count (bits 15 to 8) byte count (bits 23 to 16) byte count (bits 31 to 24) byte count (bits 7 to 0) byte count (bits 15 to 8) - - sequence state (bits 5 to 0)
Objective specification
SAA7391
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.3 DESCRIPTION OF THE HOST INTERFACE REGISTERS
SAA7391
This section describes the operation of the register bits in the SAA7391 host interface block.
7.5.3.1
ADATA
This is a 12-byte FIFO used to transfer data from the microcontroller to the host. To transfer data the `trant' bits (0 to 2) of the DTCTR register must be set to 101.
7.5.3.2
IFCTRL
Table 57 IFCTRL: address FF81H (note 1) ACCESS RW Note 1. Bits `cmdien', `dteien', `drqien' and `ultra_stopien', are the enable bits for interrupt bits `cmdi', `dtei', `drqi' and `ultra_stop' in the IFSTAT register. These are interrupt masks, enabling/disabling the microcontroller interrupt pin. They do not affect the bits in the IFSTAT register. If set to logic 1, the corresponding interrupt is enabled. It should be noted that these masks do not clear the interrupts. Bit 2 (srstien) is asserted at power-on reset, enabling the `srsti' interrupt. If set to logic 1 the `srsti' interrupt is disabled. BIT 7 cmdien BIT 6 dteien BIT 5 drqien BIT 4 ultra_stopien BIT 3 - BIT 2 srstien BIT 1 - BIT 0 -
7.5.3.3
DBCL and DBCH
These are the ATAPI byte count registers. DBCL is the lower byte (bits 7 to 0) register and DBCH is the higher byte (bits 15 to 8) register. These registers are read/writable for both the PC host and microcontroller. Table 58 ATAPI byte count registers; addresses FF82H (DBCL) and FF83H DBCH) ACCESS RW RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Data Byte Count register bits (bits 7 to 0) Data Byte Count register bits (bits 15 to 8)
The data byte counter is used by the microcontroller to control the number of bytes that are transferred during a data transfer. During memory-to-host data transfers the data byte counter is decremented after every host read. During host-to-memory data transfers the data byte counter is decremented as data is written into the external buffer memory. The host may write to DBCL/DBCH to indicate to the microcontroller the maximum transfer/reception length, which may be updated by the auto sequencer PACKETSIZE STORE registers or from the TRANSFER COUNTER (for the remainder packet size) or directly by the microcontroller. The host can then read back the updated byte count to be transferred.
7.5.3.4
DTRG
Writing to this register starts a data transfer. The data written is discarded.
7.5.3.5
DTACK
Writing to this register clears the DTEI interrupt and the `A0comp/crc_error' flag. The data written is discarded.
1997 Aug 01
38
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.3.6 RESET
SAA7391
Writing to this register resets the SAA7391 and initializes all the registers on the device. Table 59 RESET; address FF86H (note 1) ACCESS W Note 1. The `hsel' bits (see Table 60) control the mode of operation of the host interface block. After a power-on reset the `hsel' bits default to 000, i.e. the host 3-state pins are 3-stated. The firmware must configure the `hsel' bits for the desired mode of operation after every hardware reset. It should be noted that any write operation by the microcontroller to this register will result in the resetting of all other SAA7391 registers to their default condition. Table 60 Description of the `hsel' bits hsel2 to hsel0 000 001 011 100 others HOST INTERFACE MODE unknown host ATAPI generic 8-bit generic 16-bit reserved DESCRIPTION all host pins 3-state, default after hardware reset ATAPI Interface mode generic interface mode, with 8-bit transfers generic interface mode, with 16-bit transfers for future enhancements BIT 7 BIT 6 BIT 5 reserved BIT 4 BIT 3 BIT 2 BIT 1 hsel BIT 0
7.5.3.7
ASTAT
This is the ATAPI status register. Table 61 ASTAT: address FF87H (notes 1 and 2) ACCESS RW Notes 1. The `bsy' flag bit 7 will be set to logic 1 when: a) The host writes to the ACMD register and the SAA7391 is the selected drive. b) The host writes the execute drive diagnostic command (90H) to the ACMD register. c) The host writes to the ADCTR register and sets the `srst' bit. d) There is a hardware reset. 2. If a host interrupt is asserted then it will be cleared by writing to this register. BIT 7 bsy BIT 6 drdy BIT 5 dmar BIT 4 dsc BIT 3 drq BIT 2 corr BIT 1 reset BIT 0 check
7.5.3.8
ITRG
In the ATAPI mode writing to this register generates a PC host interrupt on the INT pin. This interrupt is cleared when the PC host reads the ATAPI status register (ASTAT) or writes to the ATAPI command register.
7.5.3.9
ADRADR
This is the ATAPI drive address register for the SAA7391. This uses an obsolete register address (CS1 DA0 = 10111) from the ATAPI register map in the ATAPI specification. Bit 7 of this register is high-impedance when read by the host. After a reset the ATAPI registers are all cleared except for the ASTAT register which has its `bsy' bit set.
1997 Aug 01
39
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.3.10 ASAMT
SAA7391
This is the ATAPI SAM TAG byte register.
7.5.3.11
DTCTR
The DTCTR register controls data transfer flows in the host interface block. When reset this register is cleared to all zeros except for the `rdrv' bit which is set to logic 1. This means the SAA7391 will be then set to device 1 (slave) after a reset. There are several possible data transfers through the SAA7391 host interface block and these are selected using the `trant' bits. The transfers are described in Table 64. Table 62 DTCTR: address FF8BH (see Tables 63 and 64) ACCESS RW BIT 7 reserved BIT 6 dmamode BIT 5 dma BIT 4 ultra_dma BIT 3 rdrv BIT 2 BIT 1 trant BIT 0
Table 63 Description of the DTCTR register bits BIT 6 NAME dmamode DESCRIPTION DMA mode select; controls whether the DMA transfer is single word or multi-word dmamode = 1; host Interface DMA data transfers are multi-word dmamode = 0; host Interface DMA data transfers single word 5 dma this bit is used to configure the SAA7391 hardware for either a DMA type transfer or a PIO type transfer dma = 1; configures the SAA7391 for a DMA transfer dma = 0; configures the SAA7391 for a PIO type transfer 4 ultra_dma this bit configures the SAA7391 for ultra DMA transfers; the SAA7391 must also be configured for multi-word DMA transfers for correct operation of ultra DMA i.e. bits 5 and 6 of the DTCTR register must also be set to logic 1 to select ultra DMA ultra_dma = 1; configure the SAA7391 for ultra DMA (must be select dma = 1 and dmamode = 1) ultra_dma = 0; default for non-ultra DMA transfers 3 rdrv this bit selects the device number: the polarity of this bit must be the same as the `drv' bit in the ATAPI drive select register (ADRSEL) in order for the SAA7391 to communicate with the PC host interface; after reset the microcontroller should configure the `rdrv' bit as no default may be assumed. rdrv = 1; the SAA7391 is device 1 i.e slave rdrv = 0; the SAA7391 is device 0 i.e master
1997 Aug 01
40
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 64 Description of the `trant' bits trant (bits 2 to 0) 000 001 010 011 100 101 11X FROM - host microcontroller memory host microcontroller reserved TO host memory memory microcontroller microcontroller host reserved MAXIMUM BYTES 65535 (ATAPI, PIO) 65535 (ATAPI, PIO) - - 12 12 reserved NOTES
SAA7391
maximum bytes for auto sequence DMA is 4.3 Gbytes maximum bytes for auto sequence DMA is 4.3 Gbytes redundant redundant PIO; DBC not used, always 12 bytes DMA and PIO -
7.5.3.12
ADRSEL
This is the ATAPI drive select register. Table 65 ADRSEL: address FF8CH ACCESS RW Note 1. Bit 4 of this register is the `drv' bit. When this bit is the same as the `rdrv' bit in the DTCTR register then the SAA7391 will be the selected ATAPI drive and will respond to commands and produce interrupts. The host interrupt pin will also be enabled when the SAA7391 is the selected drive. BIT 7 1 BIT 6 1 BIT 5 1 BIT 4 drv(1) BIT 3 - BIT 2 - BIT 1 - BIT 0 -
7.5.3.13
AINTR
This is the ATAPI interrupt reason register. See the ATAPI specification for a detailed description of these register bits. Table 66 AINTR: address FF8DH ACCESS RW BIT 7 - BIT 6 - BIT 5 - BIT 4 - BIT 3 - BIT 2 release BIT 1 io BIT 0 cod
7.5.3.14
AERR
This is the ATAPI error register. See the ATAPI specification for a detailed description of these register bits. Table 67 AERR: address FF8EH ACCESS RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 mcr BIT 2 abrt BIT 1 eom BIT 0 -
sense key
1997 Aug 01
41
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.3.15 ACMD
SAA7391
This is the ATAPI command register. This register is read-only to the microcontroller and write-only to the host. The host should only write to this register when the `bsy' and `drq' flags are both zero (see ASTAT register; Section 7.5.3.7). A `cmdi' interrupt is generated when: * The host writes to this register while the SAA7391 is the selected drive (the `drv' bit in register ADRSEL is equal to the `rdrv' bit in register DTCTR) * The host writes the execute drive diagnostic command (90H) to this register. The microcontroller interrupt (cmdi) is cleared by the SAA7391 when the ACMD register is read by the microcontroller.
7.5.3.16
ADCTR
This is the ATAPI device control register. Table 68 ADCTR: address FF90H ACCESS R Notes 1. Setting the `srst' bit causes a `srsti' interrupt and the `bsy' bit to be set. 2. Bit `nien' is used to enable or disable the host interrupt. When `nien' is logic 0 and the drive is selected then the host interrupt pin will be enabled. If `nien' is logic 1 or the drive is not selected then the host interrupt pin will be in a high-impedance state. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 1 BIT 2 srst(1) BIT 1 nien(2) BIT 0 0
reserved
7.5.3.17
AFEAT
This is the ATAPI features register. See the ATAPI specification for a detailed description of these register bits. Table 69 AFEAT: address FF91H ACCESS R BIT 7 - BIT 6 - BIT 5 - BIT 4 - BIT 3 - BIT 2 - BIT 1 overlap BIT 0 dma
7.5.3.18
IFSTAT
Table 70 IFSTAT: address FF92H (note 1); see Table 71 ACCESS RW Notes 1. All interrupts may be negated by writing a logic 1 to their associated IFSTAT locations. 2. These bits are flags which do not generate interrupts. BIT 7 cmdi BIT 6 dtei BIT 5 drqi BIT 4 ultra_stop BIT 3(2) dtbsy BIT 2 srsti BIT 1(2) reset08 BIT 0(2) a0comp/ crc_error
1997 Aug 01
42
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 71 Description of the IFSTAT register bits BIT 7 NAME cmdi DESCRIPTION
SAA7391
Command interrupt: in the ATAPI mode this bit is asserted when the PC host has written to the ATAPI command register (see ACMD register; Section 7.5.3.15) and the drive is selected. It is also asserted when the host writes the execute drive diagnostic command (90H) to the ATAPI command register, regardless of whether the drive is selected. It is negated when the microcontroller reads the ACMD register or writes logic 1 to `cmdi'. Data transfer end interrupt: this bit is asserted at the end of data transfer. It is negated when the microcontroller writes to the DTACK register or writes logic 1 to `dtei'. If the ATAPI mode is selected this bit is also asserted when a packet command has been received and after a microcontroller memory transfer. The interrupt generated by this bit can be masked by the auto sequencer. Auto sequencer data request interrupt: if enabled by `drqien' (IFCTRL; see Table 57), this bit is asserted after every load of the packet size store into DBCH/DBCL during an `autodrq' DMA sequence. `drqi' is cleared along with its associated interrupt by the microcontroller writing logic 1 to `drqi'. Ultra ATA stop before end of transfer interrupt: if enabled by `ultra_stopien' (IFCTRL; see Table 57), this bit is asserted if the host stops an ultra ATA data transfer before the TRANSFER COUNTER has reached zero, when `autodrq' is selected, or before the DBCH/DBCL task file registers reach zero when `autodrq' is not selected. `ultra_stop' is cleared along with its associated interrupt by the microcontroller writing logic 1 to `ultra_stop' (IFSTAT; see Table 70). Data transfer busy: this bit indicates if a data transfer is taking place. It is asserted by writing to the DTRG register and is negated at the end of the transfer. Interrupt/status transfer busy: in ATAPI mode this bit is asserted when the host writes to the ATAPI device control register and sets the `srsti' bit. It is negated when the microcontroller reads the ADCTR register or by writing a logic 1 to the `srst' (ADCTR; see Table 68). It should be noted that if this bit is asserted in the ATAPI mode then the microcontroller interrupt will also be asserted. The `srsti' interrupt cannot be disabled. The reset command 08 has been received: this bit indicates that the last command received was the 08 reset command. Reading the command register ACMD will negate this bit and its associated interrupt. The A0 command auto sequence is completed or ultra ATA CRC error flag: this bit indicates that A0 command auto sequence is completed i.e. the correct A0 command has been read and the host interface has been configured to receive the 12 byte packet. This bit does generate an interrupt but should be used in conjunction with the `dtei' interrupt. A microcontroller write to DTACK will negate the `a0comp' bit. After an ultra DMA data transfer (read from the SAA7391 or write to the SAA7391) this bit may be used in conjunction with the DTEI interrupt to indicate data integrity. If the `crc_error' bit = 0 then the last data transfer was corrupt. Again writing to DTACK will negate this bit.
6
dtei
5
drqi
4
ultra_stop
3 2
dtbsy srsti
1
reset08
0
a0comp/ crc_error
7.5.3.19
APCMD
During the ATAPI mode this register is used to read the packet command sent by the host. The packet command can only be received if the appropriate mode has been selected (see DTCTR register; Table 62) and a data transfer has been started (see DTRG register; see Table 56).
1997 Aug 01
43
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.3.20 HICONF0
SAA7391
This is the host interface configuration register 0 Table 72 HICONF0: address FF94H ACCESS RW BIT 7 BIT 6 ultractrl2 to ultractrl0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 shadow
dynhosthiprior
hrequest
Table 73 Description of the HICONF0 register bits BIT 7 to 5 4 NAME ultractrl2 to ultractrl0 dynhosthiprior dynhosthiprior (1) 0 = N = Dynamic Host High Priority asserted when FIFO is 13 full 1 = N = Dynamic Host High Priority asserted when FIFO is 12 full 3 dynhosthiprior dynhosthiprior (0) 0 = (default) dynamic host high priority off 1 = dynamic host high priority on when FIFO bytes, N, off when > N 2 and 1 hrequest hrequest = 00; (default) assert host request when FIFO 23 full hrequest = 01; assert host request when FIFO 12 full hrequest = 10; assert host request when FIFO 13 full hrequest = 11; assert host request when FIFO (full - 2 bytes) 0 shadow shadow enable: this bit controls whether shadowing of single drive configurations is enabled shadow = 1; enables shadowing for single drive configurations when the SAA7391 is master and slave is non existent shadow = 0; disables shadowing DESCRIPTION ultra control bits (3 to 1), see Section 7.5.3.22
7.5.3.21
HICONF1
This is the host interface configuration register 1. Table 74 HICONF1: address FF95H (see Table 75) ACCESS RW BIT 7 dmaen BIT 6 shhpbit BIT 5 udmaoff BIT 4 flushfifo BIT 3 - BIT 2 unmaskdtei BIT 1 clear_reg BIT 0 ultractrl3
1997 Aug 01
44
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 75 Description of the HICONF1 register bits BIT 7 NAME dmaen DESCRIPTION
SAA7391
DMA suspend: this bit controls whether DMA transfers in generic mode are suspended dmaen = 1; host Interface DMA data transfers in generic can be temporarily interrupted dmaen = 0; host Interface DMA data transfers in generic mode cannot be suspended
6
shhpbit
this bit allows statistical host high priority to be turned off shhpbit = 0; (default) statistical host high priority turned on shhpbit = 1; statistical host high priority turned off
5
udmaoff
this bit allows `udma' to be turned off at the end of a transfer udmaoff = 0; (default) switch off the `ultra_ata' bit in the DTCTR register udmaoff = 1; do nothing
4
flushfifo
Flush 12-byte command FIFO: writing a logic 1 to this bit will `flush' clear the command FIFO pointer to zero. Clearing the pointer is required if a spurious command is received while the FIFO is being loaded and is also used to ensure a 12-byte command read by the auto sequencer. flushfifo = 1; writing a logic 1 clears the FIFO pointer to zero flushfifo = 0; do nothing
2
unmaskdtei Unmask data transfer end interrupt during `autodrq' sequence: this bit will disable the auto sequencer masking of the `dtei' interrupts during the `autodrq' sequence. The `dtei', bit 6 of the IFSTAT register is not effected by `unmaskdtei'. If `unmaskdtei' is asserted the sequencer on detecting the next `dtei' interrupt, will set the `bsy' flag, negate the `drq' flag and suspend operation. The microcontroller may then reconfigure the host interface before negating unmaskdtei bit. When `unmaskdtei' is negated the sequencer will negate the `dtei' interrupt and operate as normal. unmaskdtei = 1; disable `autodrq' sequencer masking of `dtei' interrupts and suspend the sequence operation on next `dtei' interrupt unmaskdtei = 0; no effect, or restart `autodrq' sequencer operation
1
clear_reg
Clear auto sequencer transfer counter and packet size store to zero: this bit will clear the transfer counter and packet size store to zero if a logic 1 is written to it. After the write operation the registers operate as normal and the `clear_reg' bit will have no effect unless written to again. clear_reg = 1; clears to zero transfer counter and packet size store clear_reg = 0; no effect
0
ultractrl3
ultra control bit 3; see Section 7.5.3.22
1997 Aug 01
45
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.3.22 Description of the ultra control bits
SAA7391
When the SAA7391 system clock is 33.8688 MHz, maximum data transfer rates in ultra DMA Mode 0 are achieved by setting `ultractrl' to (0001). For information on meeting Mode 0 timings for system clocks other than 33.8688 MHz, please consult the user manual or product support.
The `ultractrl' register bits can be used to add system clock cycles to various timing limits used in the host interface ultra DMA transfer engine. This enables the SAA7391 to meet ultra DMA Mode 0 timings when the SAA7391 system clock is higher than 33.8688 MHz.
7.5.3.23
HISEQ
Table 76 HISEQ: host interface sequencer register; address FF96H (see Table 77) ACCESS RW BIT 7 autoa0 BIT 6 autodrq BIT 5 comp BIT 4 error BIT 3 sus_seq BIT 2 repeat autoa0 BIT 1 - BIT 0 -
Table 77 Description of the HISEQ register bits BIT 7 NAME autoa0 DESCRIPTION automatic A0 packet transfer enable: this bit enables the sequencer to automatically handle transfer of A0 packet bytes autoa0 = 1; enables automatic transfer of A0 packet bytes autoa0 = 0; disables automatic transfer of A0 packet bytes enables the auto data request sequence: this bit enables automatic handling of data requests in PIO and DMA mode transfers autodrq = 1; auto sequencer is enabled to perform auto data requests autodrq = 0; auto sequencer is not enabled to perform auto data request Completion sequence for `autodrq': this bit indicates that the auto completion sequence should be performed after the last data transfer. This bit is only valid when the auto sequencer is enabled. comp = 1; enable the auto sequencer to automate the completion sequence comp = 0; disable the auto completion sequence completion sequence with error status: this bit is copied to the check bit of the ASTAT register just before an auto completion sequence is performed error = 1; completion sequence with error status in check bit of ASTAT error = 0; completion without error status Suspend auto sequence: this bit suspends the auto sequencer for debug. If the suspend state is a write to register state then the write operation will only take place when after the `sus_seq' bit is negated. sus_seq = 1; suspend sequencer in present state sus_seq = 0; normal sequence operation Repeat the A0 packet reception auto sequence after an `autodrq' or auto completion sequence. This bit, if set before an `autodrq' or auto completion sequence, will be copied to `autoa0' bit when the sequencer is reset at the end of an `autodrq' or auto completion sequence. This bit is negated at the end of the `autoA0' sequence. Its effect is to repeat the `autoA0' sequence one more time only. It should be noted that this bit is only available on RODAP and not the M1 data base. repeat autoa0 = 1; repeat `autoA0' sequencer after `autodrq' or auto completion repeat autoa0 = 0; no effect
6
autodrq
5
comp
4
error
3
sus_seq
2
repeat autoa0
1997 Aug 01
46
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.3.24 SHSTAT
SAA7391
Table 78 SHSTAT: shadow status register; address FF97H ACCESS W Note 1. Shadow check bit: `shcheck' is the ATAPI CHECK bit in the slave shadow status register for the non-existent drive. a) 1 = Indicates an error has occurred. b) 0 = Indicates no error has occurred. BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 shcheck(1)
7.5.3.25
SHERR
Table 79 SHERR: shadow error register; address FF98H ACCESS W Note 1. Shadow abort bit: `shabrt' is the ATAPI `abrt' bit in the slave shadow error register for the non-existent drive. This bit will be read by the host in shadow mode only. a) 1 = indicates requested command has been aborted. b) 0 = indicates requested command successful. BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 shabrt(1) BIT 1 0 BIT 0 0
7.5.3.26
HIDEV
Table 80 HIDEV: host interface device register; address FF99H (see Table 81) ACCESS RW BIT 7 pdiag out BIT 6 pdiag enable BIT 5 dasp out BIT 4 dasp enable BIT 3 pdiag in BIT 2 dasp in BIT 1 - BIT 0 hosthipi
1997 Aug 01
47
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 81 Description of the HIDEV register bits BIT 7 NAME pdiag out DESCRIPTION
SAA7391
6
pdiag pad enable
5
dasp out
4
dasp pad enable
3 2 0
pdiag in dasp in hosthipi
this bit is the passed diagnostics signal output from the SAA7391 pdiag out = 1; writing logic 1 to this bit drives the PDIAG pin HIGH if the pad enable (`pdiag enable' bit 6) is set to logic 1. It is recommended that this bit is written LOW and that the enable bit is driven to emulate an open-collector output. pdiag out = 0; writing logic 0 to this bit sets the PDIAG pin LOW if the pad enable (`pdiag enable' bit 6) is set to logic 1 this bit default is an input to the SAA7391 pdiag pad enable = 1; writing logic 1 to this bit enables the PDIAG driver output of the SAA7391 pdiag pad enable = 0; default on power-up allowing external control of the `pdiag in' bit 3 This bit is the device active slave present signal output. This pin is open-collector with an external pull-up resistor. The DASP bit must be set to logic 1 in order to determine if any other device is driving this signal. dasp out = 1; writing logic 1 to this bit drives DASP HIGH if the pad enable (`dasp enable' bit 4) is set to logic 1. It is recommended that this bit is written LOW and that the enable bit is driven to emulate an open-collector output. dasp out = 0; writing logic 0 to this bit sets the DASP pin LOW if the pad enable (dasp enable bit 4) is set to logic 1 this bit default is an input to the SAA7391 dasp pad enable = 1; writing logic 1 to this bit enables the DASP driver output of the SAA7391 dasp pad enable = 0; default on power-up allowing external control of the dasp in bit 2 this bit is the passed diagnostics signal input to the SAA7391, only valid if `pdiag enable' bit 6 is set to logic 0 (default = 0) this bit is the device active slave present signal input to the SAA7391, only valid if `dasp enable' bit 4 is set to logic 0 (default = 0) This bit allows the host interface to increase its priority rating when requesting a data transfer between itself and the SAA7391 memory processor. With host high priority set the host data transfer requests are given the second highest priority, the highest given to the microcontroller. hosthipi = 1; writing logic 1 increase host interface priority above all other data transfer requests, bar the microcontroller. hosthipi = 0; writing logic 0 to this bit (default setting) gives low priority to the host interface data transfer request.
1997 Aug 01
48
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.4 TRANSFER COUNTER
SAA7391
The transfer counter register defines the total transfer length to be transferred to or from the host. This register is loaded by the microcontroller and decrements synchronously with the DBCH/DBCL registers. The remainder packet size can be loaded from the transfer counter into DBCH or DBCL when the transfer counter value becomes less than the packet size store. Table 82 Transfer counter register ADDRESS FFA0H FFA1H FFA2H FFA3H 7.5.5 ACCESS RW RW RW RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
byte count (bits 7 to 0) byte count (bits 15 to 8) byte count (bits 23 to 16) byte count (bits 31 to 24)
PACKET SIZE STORE
The packet size store will be loaded from the DBCH or DBCL registers when the host writes to ACMD, provided the drive is selected. It may also be updated by the microcontroller. The DBCH/DBCL registers will be auto loaded from the packet size store on condition that the transfer counter contains an equal or greater value than that held in the packet size store. Table 83 Packet size store ADDRESS FFA4H FFA5H 7.5.6 ACCESS RW RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
byte count (bits 7 to 0) byte count (bits 15 to 8)
SEQUENCER STATUS
7.5.6.1
Sequencer status
For debugging the auto sequencer a sequencer status register has been provided (address FF6AH). A suspend sequence bit has been provided (`hiseq' bit 4; see Table 76), which if asserted (logic 1) will suspend the auto sequencer operation at its present state. The suspended state may then be read from the sequencer state register. If the sequencer state is a write to a host interface registers state, then the sequencer will perform the write operation after the suspend sequencer bit is negated by the microcontroller. Table 84 Sequencer status: address FFA6H (note 1) ACCESS R Note 1. For an explanation of the sequence state number see the user guide. The user guide is available from product support. BIT 7 - BIT 6 - BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
sequencer state (bits 5 to 0)
1997 Aug 01
49
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.6.2 Auxiliary block memory processor registers
SAA7391
An interrupt is associated with HOSTBYTECOUNT becoming zero. This is an indication to the microcontroller to reload the HOSTCURSEG and HOSTBYTECOUNT registers for the next transfer. The HOSTCURSEG, HOSTBYTEOFFSET and HOSTBYTECOUNT registers indicate the address of the next byte to be transferred to or from the host, in order that the status of the interface may be read. The operation of the HOSTBYTECOUNT and HOSTBYTEOFFSET registers is given in Table 85.
The registers given in Table 85 are located in the Aux block of the and control the SAA7391 memory processor buffer management. Transfer to/from the host is possible as soon as the HOSTBYTECOUNT is non-zero, and the HOSTCURSEGCNT is non-zero. The `chan0' and `chan1' bits control the sequencing of sub-block transfers. They indicate the number of offset/length pairs to use for each block being transferred. Normally only channels 0 and 1 are needed for Mode 2 host transfers. Channels 2 and 3 are available for special READ-CD command options. Table 85 Host interface DMA pointers ADDR FF45H FF44H FF66H FF59H FF58H FF5DH FF5CH FF51H FF50H FF55H FF54H FF5BH FF5AH FF5FH FF5EH FF53H FF52H FF57H FF56H FF43H FF42H FF65H FF64H FF69H FF68H FF6BH ACCESS RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW NAME HOSTCURSEG-L HOSTCURSEG-H HOSTCURSEGCNT HOSTSUBBLKOFFSET0-L HOSTSUBBLKOFFSET0-H HOSTSUBBLKOFFSET1-L HOSTSUBBLKOFFSET1-H HOSTSUBBLKOFFSET2-L HOSTSUBBLKOFFSET2-H HOSTNEXTSEG-L HOSTNEXTSEG-H HOSTSUBBLKCOUNT0-L HOSTSUBBLKCOUNT0-H HOSTSUBBLKCOUNT1-L HOSTSUBBLKCOUNT1-H HOSTSUBBLKCOUNT2-L HOSTSUBBLKCOUNT2-H HOSTNEXTSEGCOUNT HOSTRELOADFLAGS HOSTBYTEOFFSET-L HOSTBYTEOFFSET-H HOSTBYTECOUNT-L HOSTBYTECOUNT-H HOSTRELSEG-L HOSTRELSEG-H AUX_FORM_SCAN
BIT 7 s7 chan1 b7 a7 autoform a7 autoform a7 autoform a7 autoform c7 - c7 - c7 - c7 rel1 a7 autoform c7 - s7 chan1 c7
BIT 6 s6 chan0 b6 a6 form a6 form a6 form a6 form c6 - c6 - c6 - c6 rel2 a6 form c6 - s6 chan0 c6
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 s5 - b5 a5 - a5 - a5 - a5 - c5 - c5 - c5 - c5 - a5 - c5 - s5 - c5 s4 s12 b4 a4 - a4 - a4 - a4 a12 c4 - c4 - c4 - c4 - a4 - c4 - s4 s12 c4 s3 s11 b3 a3 a11 a3 a11 a3 a11 a3 a11 c3 c11 c3 c11 c3 c11 c3 c11 a3 a11 c3 c11 s3 s11 c3 s2 s10 b2 a2 a10 a2 a10 a2 a10 a2 a10 c2 c10 c2 c10 c2 c10 c2 c10 a2 a10 c2 c10 s2 s10 c2 s1 s9 b1 a1 a9 a1 a9 a1 a9 a1 a9 c1 c9 c1 c9 c1 c9 c1 c9 a1 a9 c1 c9 s1 s9 c1 s0 s8 b0 a0 a8 a0 a8 a0 a8 a0 a8 c0 c8 c0 c8 c0 c8 c0 c8 a0 a8 c0 c8 s0 s8 c0
1997 Aug 01
50
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 86 Decoding `chan' bits VALUE 00 01 10 11 7.5.7 HOST INTERFACE DMA SPECIAL BITS DESCRIPTION use extent 0 use extent 0 to 1 use extent 0 to 2 use extent 0 to 3 (see also Section 7.5.8)
SAA7391
Table 87 Decoding bits 7 and 6 of HOSTSUBBLKOFFSETX-H (note 1) BIT 7 6 NAME autoform form VALUE 0 1 0 1 Note 1. The last Form bit is the LSB of the byte that is situated at offset 12 in the current segment pointed at by HOSTCURSEG. This is the stored Form byte in the header. 7.5.8 AUTOMATIC BLOCK POINTER RELOAD
PROGRAMMING
DESCRIPTION unconditional transfer only transfer if previous Form bit matches bit 6 match last Form bit = 0, perform this transfer if success else reload host registers match last Form bit = 1, perform this transfer if success else reload host registers
7.5.9
DMA TRANSFER PROGRAMMING OF THE HOST
INTERFACE
If either bit 6 or bit 7 are set in the HOSTRELOADFLAGS register, then when the HOSTRELOADCOUNT register becomes zero, the value of HOSTCURSEGCNT will be copied from HOSTNEXTSEGCOUNT and HOSTRELSEGMENT will be copied from HOSTNEXTSEG. This causes the host transfer process to continue looping over the same region of memory in emulation of the Chaucer and Sequioia devices. At the same time one of the bits HOSTRELOADFLAGS (bits 7 and 6) is reset on reload of the registers. The other bit retains its value. Therefore: * Single auto-reload is allowed: HOSTRELOADFLAGS (bits 7 and 6) = 1 0 * No auto-reload: HOSTRELOADFLAGS (bits 7 and 6) = 0 0; pointer can be used as sub-block extent 3 * Multiple auto-reload: HOSTRELOADFLAGS (bits 7 and 6) = 0 1.
The host interface is optimized for the normal read commands, handling all data transfers or contiguous data plus header requests automatically, with auto Form detection in Mode 2. If discontinuous data which requires more than 3 sub-block extents e.g. for READ-CD is required then it is necessary to program the HOSTCURSEG, HOSTBYTECOUNT and HOSTBYTEOFFSET for each discontinuous part of each block that is to be transferred. Writing the value 1 into the `hostblock' will cause the transfer to take place.
1997 Aug 01
51
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.10 GENERIC INTERFACE OPERATION
SAA7391
The active LOW Chip Select (CS) signal from the SAA7391 is generated by the host interface. There are 32 specific SCSI addresses in the SAA7391 memory map, between location FFC0H and FFDFH. The CS pin will be active LOW for addresses in this range. The standard register set on the NCR 53CF92 contains 16 registers which are accessed when the CS is true. The specific register being accessed is determined by the states of the RD and WR signals together with the address pins A3 to A0.
Implementation of the generic interface with the NCR 53CF92 in a multiplexed bus configuration is shown in Fig.4. The host interface, after power-up, needs to be configured for the SCSI controller by writing the value 3 to the RESET register (address FF86H) for an 8-bit data transfer configuration and the value 4 for a 16-bit data transfer configuration. The NCR 53CF92 device is configured by tying it's mode pin to ground. In this mode the NCR 53CF92 device expects from the microcontroller a multiplexed address/data bus. Multiplexed address/data bus is the only mode supported by the SAA7391.
handbook, full pagewidth
DMACK/DMARQ DMARQ/DMACK DA1/DBWR 8-bit DMA bus DD0 to DD7
DREQ DACK DBWR DB7 to DB0 A0 A1
SAA7391
DA2/DBRD
NCR 53CF92
A2/DBRD A3/ALE
CS0/SCSICS
CS
8051
MICROCONTROLLER 8-bit address/data bus
RD WR
MODE
MGK508
Fig.4 Generic interface connection to NCR 53CF92 in multiplexed mode.
1997 Aug 01
52
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.5.11 DMA TRANSFERS IN GENERIC MODE 7.5.12 NORMAL DMA MODE
SAA7391
The host interface in generic mode will support two types of DMA transfer to the NCR device, namely: * Normal DMA mode * Burst DMA mode. Both of these modes are 8 bit DMA transfers. During data transfers the microcontroller can suspend the DMA transfer (via HICONF1 register `dmaen' bit 7) under the following conditions: * An Interrupt received * An abort received * A register read required.
In this mode the host Interface transfers data in single bytes. This DMA mode is configured by setting `dmamode' (DTCTR register bit 6) to zero, and DMA (DTCTR register bit 5) to one. Data flow direction and byte counts are configured the same as ATAPI DMA modes of data transfer, but with command information being received via the NCR SCSI controller registers external to the SAA7391 operation. The data transfer takes place as long as the DMA request signal DMARQ is true. The DMACK signal is toggled by the host Interface for each byte transferred as shown in Fig.5.
handbook, full pagewidth
DMARQ
DMACK
DBRD/ DBWR
MGK514
Fig.5 Generic interface normal DMA mode.
7.5.13
BURST DMA MODE USING MULTIPLEXED BUS CONFIGURATION
In this mode the DMA data is available on the DMA bus when both, DBRD or DBWR and DMACK are true. DMACK remains asserted throughout the transfer while DBRD toggles for each transfer as shown in Fig.6. To configure the host interface the DMA mode and DMA bits (DTCTR bits 6 and 5) should be set to logic 1.
1997 Aug 01
53
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
DMARQ
DMACK
DBRD/ DBWR
MGK515
Fig.6 Burst DMA mode using multiplexed bus configuration.
7.6
Microcontroller interface
This section provides a brief introduction to the software and hardware environment expected in a system using the SAA7391 device. Because all of the SAA7391 registers are randomly accessible, the processor controlling the SAA7391 is able to use interrupts. 7.6.1 KERNEL BASED FIRMWARE
The low byte is kept in a holding register and presented to the sub-CPU when the low byte is requested. Even if the sub-CPU is interrupted (and the holding register is then stacked and replaced during the service routine) the 16-bit read will be the value of the register at a single instance in time. Similarly for writing, the high byte is held in the holding register to be written later to the 16-bit register at the same time as the low byte is written to the SAA7391. Again the holding register must be saved during an Interrupt Service Routine (ISR) if the ISR itself is likely to cause any 16-bit reads or writes to take place. It should be noted that any ISR, which requires access to a 16-bit or 8-bit register in the address range FF20H to FF6FH, will overwrite the holding register and therefore its contents must be stacked before the interrupt is serviced. Furthermore, there is only one holding register that may be accessed both for reading and writing. In this way the interrupt routine can easily save data that was stored in the holding register before it was written. A single location (TEMP_DATA, register FF6FH) is used as the location to read the value of the holding register, regardless of which address was used in the original read or write process. The IRS stacking process of the holding register is illustrated in Fig.8.
It is recommended that the sub-CPU runs a multi-tasking kernel to properly support the multiple `threads' of operation that are required of it in use. Therefore the memory mapper specified in this document has the concept of having 2 pages of memory for data. Then one page of data space can be switched in to the memory map for each thread as needed, while still keeping a fixed part of the memory map for the interrupt service routines and other fixed housekeeping code and data. 7.6.2 16-BIT REGISTERS AUTOMATIC READ AND WRITE
All of the 16-bit registers provided in the SAA7391, are used by writing the Most Significant Bit (MSB) first. These registers are located in the address range FF20H to FF6FH together with some 8-bit registers. To facilitate `snapshot' reading or writing of the 16-bit register an 8-bit holding register is provided to store the `spare' byte of data. This is implemented in such a way that a 16-bit read consists of a sample of the value of the register at the instant that the high byte was read from that register.
1997 Aug 01
54
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
address bus
16-BIT REGISTER FILE A1 to An D8 to D15 Q8 to Q15 Q0 to Q7 8
A0
0 MUX 1
data bus D0 to D7 8 8 0 MUX 1 read 8-BIT HOLDING REGISTER (FF6F)
loaded when: (A0 = 0 and write) or (A0 = 0 and read)
MGK509
This is intended for big-endian high byte then low byte accesses to 16-bit register space.
Fig.7 Holding register used in 16-bit access via 8-bit bus.
program flow handbook, halfpage
interrupt
read/write high1 save register
read/write high2
read/write low1 read/write low2
restore register
MGK510
Fig.8 Stacking 8-bit holding register during interrupt service.
1997 Aug 01
55
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.7 8051 CPU and memory management functions
SAA7391
In the fast RAM access mode all external accesses below C000 are expected to be program fetches. A DRAM access cycle is not begun. Above C000, the RAM cycle begins on the falling edge of ALE hence the number of 8051 wait states can be reduced. This is not however recommended. The disadvantage is, that the RAM access cycle is started regardless of whether it will be needed. This has the effect of aborting any other on-going use of the buffer memory and reducing the available bandwidth. Consequently, the number of wait states on accessing RAM must be greater. In return, more RAM is accessible. In the slow RAM access mode the RAM access cycle starts on the falling edge of RD or WR, if PSEN is HIGH, this being the first time in the 8051 external memory access cycle that it is possible to determine that an XDATA access is in fact being made. This access mode has a lower impact on the buffer RAM memory bandwidth as only accesses that are needed are made. The two modes are under control of a register bit, and it is possible to switch between them at any time.
The 8051 CPU and memory management functions are as follows: * Device registers are memory mapped for faster direct access to the chip * Provides direct access from sub-CPU to buffer RAM to support scratchpad accesses; this eliminates the need for extra RAM chips in the system * Address space reserved for generic host interface control and status pass-through (it is shared with ATAPI register space; see Section 7.5) * Interfaces to 8051 multiplexed address and data bus * Two dynamically controllable RAM access modes allow trade-off between accessible scratchpad RAM size and RAM access time. 7.7.1 SUB-CPU BUS ACCESS TIMING
The fast and slow RAM access timing diagrams are illustrated in Figs 10 and 9. It should be noted that fast RAM access is not recommended due to its negative effect on the RAM bandwidth and the overall system performance.
handbook, full pagewidth
(1)
sub-CPU clock (2) sub-CPU ALE (3)
XDA8 to XDA15 RD/WR
XDA0 to XDA7, XDA8 to XDA15 latched
XDD0 to XDD7
MGK516
(4)
(1) (2) (3) (4)
SAA7391 accesses RAM and stops clock until complete. RD LOW or WR LOW indicates access actually taking place. 8051 microcontroller continues. Address decoded for possible access RAM.
Fig.9 Slow RAM access mode timing.
1997 Aug 01
56
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
(1)
sub-CPU clock (2) sub-CPU ALE
XDA8 to XDA15
XDA0 to XDA7, XDA8 to XDA15 latched
XDD0 to XDD7
RD/WR
MGK517
(1) Address decoded in upper 16 kbytes indicates access to RAM or SAA7391 registers, RAM access begins, SAA7391 accesses RAM, stops clock only if SAA7391 asserts RD or WR before access complete. (2) 8051 microcontroller continues.
Fig.10 Fast RAM access mode timing.
7.7.2
BUFFER MEMORY ORGANISATION
Memory is mapped as a 12-bit block number and a 12-bit offset into that block. The block oriented memory structure permits the use of 16-bit pointers in software, minimising the overhead of accessing memory. The address can be found from the following equation: address = block_number x 2560 + offset The sub-CPU sees the SAA7391 as a memory mapped peripheral, with control and status registers appearing in the highest 256 bytes of the external address space (PDATA space). The phrase (PDATA space) is meant to imply that the code will access registers most efficiently if the PDATA (8051 port P2) pointer is set to point at the register space of the SAA7391. If the PDATA space is better used as context switching space then it can be used for that purpose. All registers and RAM are accessible in the XDATA space at all times, the PDATA is just a movable 256 byte window with faster access into XDATA.
The lowest 56 kbytes of the 8051 external address data space is mappable as two windows into the memory of 52 kbytes and 4 kbytes, on any user-specified 256 byte boundary within the RAM. This is usable as scratchpad RAM. The two pages permits the paging of process context information for use with a multi-tasking kernel, while still keeping some global variables. The next 7.5 kbytes is mapped as a window into memory starting at a user-specified block number. This is usable for accessing block data, subcode information, error corrector status and block headers. The 64 kbytes memory mapping is shown in Fig.11.
1997 Aug 01
57
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
0XFF00 subseg 2 subseg 1 0XE000 0XD000 0XC000 subseg 0 subpage 2 base address is moved in terms of block number 4 kbits always accessible, base address movable in 256 byte pages top 4 kbits always visible 7.5 kbits window into 3 CD-ROM blocks
subpage 1
bottom 48 kbits not usable in fast RAM mode
0X0000
MGK511
In fast RAM mode (see `CONF_8051' bit 7) the lower 48 kbytes of RAM space is not accessible as it is reserved for external ROM.
Fig.11 Memory mapping of the SAA7391 registers into 64 kbytes sub-CPU address space.
Table 88 The SAA7391 memory map ADDRESS FFCOH to FFFFH FF00H to FFBFH E000H to FEFFH D000H to DFFFH C000H to CFFFH 0000H to BFFFH Notes 1. If the SAA7391 is addressed in this area it will not access the DRAM and the data output of the sub-CPU interface to the microcontroller is disabled. If the SAA7391 host interface has been configured for generic mode and the address access from FFC0H to FFDFH, a chip select signal is asserted `zero' on the output pin XDA1. 2. CPU address (bits 23 to 8) = 0. CPU address (bits 7 to 0) = address (bits 7 to 0). 3. Read in this segment is always from internal the SAA7391 registers. Write is to internal the SAA7391 registers and, optionally, also to DRAM if debug is set (conf_8051, bit 1 = 1). 4. CPU address (bits 8 to 0) = address (bits 8 to 0). CPU address (bits 23 to 9) = subseg 1 (bits 12 to 0) + subseg 1 (12 to 0) x 4 + address (bits 12 to 9). 5. CPU address (bits 9 to 0) = address (bits 9 to 0). CPU address (bits 23 to 10) = subseg 2 (bits 15 to 2) + address (bits 11 and 10). 6. CPU address (bits 9 to 0) = address (bits 9 to 0). CPU address (bits 23 to 10) = subseg 1 (bits 15 to 2) + address (bits 15 to 10). SEGMENT SIZE (BYTES) 64 192 7936 4096 4096 49152 USED FOR the SAA7391s dead space the SAA7391 register access, debug write to DRAM segments in DRAM subpage 2 in DRAM subpage 1 in DRAM subpage 1 in DRAM ADDRESS FUNCTION none; note 1 none; notes 2 and 3 note 4 note 5 note 6 notes 1 and 6
1997 Aug 01
58
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.7.3 SUBPAGE
SAA7391
The lowest 52 kbytes (0X000H to 0XCFFFH) of the external data memory is mapped to SUBPAGE1. If the user requires less RAM than is provided here (up to 52 kbytes), the 1024 byte granularity of positioning the offsets permits the pages to be overlapped. In the fast RAM access mode, the lowest 48 kbytes are not accessible as they are assumed to be ROM space. The next 4 kbytes (0XD000H to 0XDFFFH) of the external data memory is always mapped to SUBPAGE2, and is always available. Table 89 Subpage RAM offsets ADDRESS FF18H FF19H FF1AH FF1BH NAME SUBPAGE1-H SUBPAGE1-L SUBPAGE2-H SUBPAGE2-L BIT 7 a23 a15 a23 a15 BIT 6 a22 a14 a22 a14 BIT 5 a21 a13 a21 a13 BIT 4 a20 a12 a20 a12 BIT 3 a19 a11 a19 - BIT 2 a18 a10 a18 a10 BIT 1 a17 - a17 - BIT 0 a16 - a16 -
7.7.3.1
Sub-CPU segment page
The sub-CPU may access three adjacent segments of data offset from the base segment pointed to by `subseg'. These are mapped as a contiguous 7.5 kbytes block at the top of memory from 0XE000 to 0XF800. The buffer address is formed using the following equation: Buffer address = subseg ( down to 0 ) x 2560 + sub-CPU (a12 down to 0) This permits the writing of headers and looking at subcode information which may span more than one segment. Linked lists in the `spare' space at the end of a segment may be more easily manipulated if the segment and its neighbours are visible to the sub-CPU in a consistent manner. It is also possible to indirectly access any part of RAM by using the block copy registers to move the data to and from the sub-CPU subpages.
7.7.3.2
Sub-CPU segment page restriction
It should be noted that the SAA7391 device does not have the concept of a defined upper limit on the segment addressed block. Hence the segment page is always 3 contiguous segments of RAM, even when near or at the top of accessible RAM or at the top of the firmware defined data input buffer. In this case 1 or 2 of the blocks accessed will be beyond the buffer. Table 90 Sub-CPU segment RAM offsets ADDRESS FF1CH FF1DH 7.8 NAME SUBSEG-H SUBSEG-L BIT 7 s7 - BIT 6 s6 - BIT 5 s5 - BIT 4 s4 - BIT 3 s3 s11 BIT 2 s2 s10 BIT 1 s1 s9 BIT 0 s0 s8
External memory interface
The external memory interface is designed to operate with up to 128 Mbits hyper-page 33 MHz DRAM (EDO RAM) It is also designed to operate with fast-page DRAM giving a 17.5 Mbyte/s burst transfer rate. Figures 13 and 14 illustrate the timing diagram for fast-page mode. It should be noted that during the power-on reset cycle it is necessary to pull the XDATA bus to all zeros to configure the SAA7391 for use with the 8051 microcontroller.
1997 Aug 01
59
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.8.1 DRAM INTERFACE CONFIGURATION REGISTER
SAA7391
Table 91 DRAM_CONFIG: address FF6AH (see Table 92) ACCESS W BIT 7 - BIT 6 - BIT 5 - BIT 4 feature 4 BIT 3 feature 3 BIT 2 feature 2 BIT 1 feature 1 BIT 0 feature 0
Table 92 Description of the DRAM interface features feature 4 0 1 X X X X X feature 3 X X 1 0 X X X feature 2 X X X X 1 1 0 feature 1 X X X X 0 1 X feature 0 X X X X X X X OPTION refresh every 256 system clock cycles refresh every 511 system clock cycles minimum RAS LOW is 2 clock cycles minimum RAS LOW is 3 clock cycles 1 Mbit x 4 DRAM used 4 Mbit x 4 DRAM used 512 kbits x 8, 1 Mbit x 8, 2 Mbits x 8, 4 Mbits x 8, 8 Mbits x 8 or 16 Mbits x 8 DRAM used use fast-page mode device use hyper-page mode device
X X 7.9
X X
X X
X X
0 1
UART for communication with CD engine
The following are required for communication with the CD engine: * Clock prescaler for selectable baud rate * Synchronous slave peripheral interface * Asynchronous UART * DMA to reduce sub-CPU loading in SPI mode * Interrupt options available. 7.9.1 UART BASIC ENGINE INTERFACE
same place in the buffer for each DMA transfer it will be necessary to reload these pointers before re-enabling DMA for the data transfer. DMA operation can be independently on for the transmit and receive channels. To enable the DMA receive channel the UART_DMA_CTRL bit 7 must be set to logic 1. When the receive DMA channel is active the sub-CPU cannot read the receive register (RXDATA address FF77H) any more but the SAA7391 will automatically copy the contents of the RXDATA register to the address pointed at by the SPI_RX_OFFSET pointer if it is full, increment the SPI_RX_OFFSET pointer and reset the `rvbfull' bit. The SPI offset registers are available in both synchronous and asynchronous modes and not just for SPI. The SPI_RX_OFFSET register may be read to determine how many bytes have been received. The polarity of the SPI clock is selectable from the UARTCOM register (see Table 94). To enable the DMA transmit channel the UART_DMA_CTRL bit 6 must be set to logic 1 and, at the same time, bits 5 to 0 (`txdmacount') must be greater than zero. When the transmit channel is active the sub-CPU can write to the transmit register (TXDATA address FF77H), however, the SAA7391 will automatically perform the following operation. 60
The basic engine interface implements both a synchronous peripheral interface and an asynchronous high-speed serial interface. The same registers are shared between the functions involved. Transmitted and received data in asynchronous mode is sent or received with parity bits in 8-bit, one parity bit, one STOP bit format. The registers that are implemented are described below. Two 16-bit DMA pointers (SPI_RX_OFF and SPI_TX_OFF) are provided so that the interface may be used in a DMA mode. As a byte is transferred to or from the UART registers, it is possible to copy it into a part of the AUXSEG RAM (16-bit register AUXSEGMENT-H or AUXSEGMENT-L) in the SAA7391s buffer memory. The pointers auto-increment and wrap within the region assigned, so if the user wishes the data to appear in the 1997 Aug 01
If (transmit register empty) TRANSMITREG = RAM [AUXSEGMENT x 2560 + SPI_TX_OFFSET]
1997 Aug 01 61
Philips Semiconductors
ATAPI CD-R block encoder/decoder
SPI_TX_OFFSET = SPI_TX_OFFSET + 1 uart_dma_ctrl (5 : 0) = uart_dma_ctrl (5 : 0) - 1 end if; Transmission will automatically stop when the `uart_dma_ctrl' (bits 5 to 0) (the `txdmacount') has incremented to zero. This condition will produce the interrupt. Data transmission rates are selectable by writing a value n(0 to 255) to the UART_PRE_SCALER register. The baud rate for each mode can then be calculated as follows: f sysclk For the SPI mode f SPI = ----------------------------------[ 2 x ( n + 1) ] f sysclk For the S2B mode f S2B = -------------------------------------[ 16 x ( n + 1 ) ] Table 93 UART general registers ADDRESS FF28H FF29H FF4AH FF4BH FF4CH FF4DH FF74H FF75H FF76H FF77H FF7H FF78H FF79H FF7EH FF7FH Notes 1. See Table 95. 2. See Table 96. NAME AUXSEGMENT-H AUXSEGMENT-L SPI_RX_OFF-H SPI_RX_OFF-L SPI_TX_OFF-H SPI_TX_OFF-L UART_PRE_SCALER (rw)7 UART_DMA_CTRL (rw) UARTCOM (w) RXDATA (w) RXDATA (r) UARTTINTSTAT/RESET (rw) UARTTINTEN (w) UARTSTAT (r)(1) UARTAUXSTAT (r)(2) BIT 7 bit 15 bit 7 bit 15 bit 7 bit 15 bit 7 rcvdma on paron d7 d7 comsync comsyn comsync comiack BIT 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 txdma on spion d6 d6 syssync syssync syssync txfull BIT 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 BIT 4 BIT 3 BIT 2 BIT 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 BIT 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0
-
bit 12 bit 11 bit 10 bit 4 bit 3 bit 2 bit 12 bit 11 bit 10 bit 4 bit 3 bit 2 bit 12 bit 11 bit 10 bit 4 bit 3 bit 2 prescale value (bits 7 to 0) txdmacount (bits 5 to 0) - - - d4 d4 not syssync not syssync syssync - d3 d3 not txbfull not txbfull txbfull - d2 d2 rvbfull rvbfull rxbfull -
- d1 d1 overrun overrun overrun -
d5 d5 not comsync not comsync comsync rxfull
parpol clkpol d0 d0 rvparity rvparity rxparity -
Objective specification
SAA7391
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 94 Description of the UARTCOM register bits BIT 7 6 0 NAME paron spion parpol clkpol VALUE 0 1 0 1 0 1 disable parity bit in S2B mode enable parity bit in S2B mode S2B transmission mode SPI transmission mode SPI clock active LOW; S2B even parity SPI clock active HIGH; S2B odd parity DESCRIPTION
SAA7391
Table 95 Description of the UARTSTAT register bits BIT 7 6 5 4 3 2 1 0 NAME comsync syssync comsync syssync txbfull rxbfull overrun rxparity VALUE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - transmit data buffer is empty and ready for another byte receive data buffer is not valid receive data buffer is valid - a byte was lost because the `rxdata' register was not read in time - received parity bit is in error inverted syssync pin level inverted comsync pin level syssync pin level comsync pin level DESCRIPTION
Table 96 Description of the UARTAUXSTAT register bits BIT 7 6 5 NAME comiack txfull rxfull VALUE 0 1 0 1 0 1 - transmit register is full (a byte is being sent) - receive register holds a byte, need to read a byte immediately to avoid overrun comiack pin level DESCRIPTION
Table 97 CD playback error rate measurement registers ADDRESS FF11H FF12H NAME C1BLERCNT C2BLERCNT BIT 7 d7 d7 BIT 6 d6 d6 BIT 5 d5 d5 BIT 4 d4 d4 BIT 3 d3 d3 BIT 2 d2 d2 BIT 1 d1 d1 BIT 0 d0 d0
1997 Aug 01
62
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.10 7.10.1 Clock generation control CRYSTAL OSCILLATOR
SAA7391
The crystal oscillator is a conventional 2-pin inverting design operating from 8 to 35 MHz; this oscillator is also capable of operating with a 33.8 MHz ceramic resonator. It is capable of oscillating with both fundamental and 3rd-overtone mode crystals. External components should be used to suppress the fundamental output of the 3rd-overtone types as shown in Fig.12. When operating with lower frequency crystals, Rs must be greater than 0 to avoid overdriving the crystal.
handbook, halfpage
SAA7391
oscillator
CROUT Rs (0 ) 34 MHz
CRIN
3.3 H 1 nF
100 k 10 pF 10 pF
MGK512
Fig.12 Clock oscillator application circuit for 3rd-overtone crystal.
1997 Aug 01
63
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
7.10.2 SUB-CPU CLOCK CONTROL REGISTER
SAA7391
This register controls the clocking of the sub-CPU and the generation of wait states, ensuring a low jitter in the clock while allowing wait states. Table 98 CONF_8051: address FF73H (see Table 99) BIT 7 modsel BIT 6 wait2 BIT 5 wait1 BIT 4 wait0 BIT 3 div2 BIT 2 div1 BIT 1 div0 BIT 0 debug
Table 99 Description of the CONF_8051 register bits BIT 7 6 to 4 NAME modsel wait2 to wait0 VALUE 0 1 000 001 010 011 100 101 110 111 3 to 1 div2 to div0 000 001 010 011 100 1XX 0 debug 0 1 Note 1. The clock pulse provided to the 8051 is equal to the HIGH period of sysclk for divide-by-1 and divide-by-1.5. For all other division ratios the clock pulse HIGH time is equal to one cycle of sysclk. 7.10.3 SAA7391 SYSTEM CLOCK CONTROL REGISTERS 0 wait states 1 wait state 2 wait states 3 wait states 4 wait states 5 wait states 6 wait states 7 wait states 8051 clock is sysclk; note 1 8051 clock is sysclk/1.5; note 1 8051 clock is sysclk/2 8051 clock is sysclk/3 8051 clock is sysclk/4 undefined - register writes are shadowed through into buffer RAM wait state control DESCRIPTION
Table 100 CLK_CON register ADDRESS FF9EH FF9FH Note 1. Write operations to bit 6 of CLK_CON register may become unreliable once this bit has been written to with a logic 1. NAME MULTI_CON CLK_CON(1) BIT 7 mode pllpwr BIT 6 m6 pllena BIT 5 m5 - BIT 4 m4 - BIT 3 m3 - BIT 2 m2 - BIT 1 m1 xtal1 BIT 0 m0 xtal0
1997 Aug 01
64
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 101 Description of the CLK_CON register bits BIT 7 6 1 and 0 NAME pllpwr pllena xtal1 and xtal0 VALUE 0 1 0 1 00 01 10 11 DESCRIPTION PLL is powered-down PLL is powered-up system clock source is CRIN system clock source is from clock multiplier crystal is 8.4672 MHz; divide-by-16 crystal is 11.289 MH; divide-by-22 crystal is 16.9344 MHz; divide-by-32 crystal is 33.8688 MHz; divide-by-64
SAA7391
fPLL (kHz) - - - - 529.2 513.1 529.2 529.2 -
NOTES default default - - - default -
Table 102 The relationship between the values of the m bits and VCO frequency for a normalised PLL frequency of 500 kHz; note 1 m6 to m0 (HEX) 02 04 08 11 22 44 09 13 26 4C 18 31 62 45 0B 17 2E 5D 3A 75 6B 56 2D 5B 36 6C 1997 Aug 01 FREQUENCY (MHz) 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 65 m6 to m0 (HEX) 58 30 60 41 03 06 0C 19 33 66 4D 1A 35 6A 54 29 53 27 4E 1C 39 73 67 4F 1E 3D FREQUENCY (MHz) 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
m6 to m0 (HEX) 7B 76 6D 5A 34 68 50 21 42 05 0A 15 2A 55 2B 57 2F 5F 3E 7D 7A 74 69 52 25 4A 14 28 51 23 46 0D 1B 37 6E 5C 38 71 63 47 1997 Aug 01
FREQUENCY (MHz) 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 66 Note
m6 to m0 (HEX) 0F 1F 3F 7F 7E 7C 78 70 61 43 07 0E 1D 3B 77 6F 5E 3C 79 72 65 4B 16 2C 59 32 64 49 12 24 48 10 20 40
FREQUENCY (MHz) 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
1. It should be noted that the mode bit (MSB high byte) has not been included in the table. The oscillator output frequency can be determined by dividing the VCO frequency given in Table 102 according to the mode bit described in Table 103.
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 103 Explanation of mode bit MODE BIT 0 1 DIVISION RATIO divide the frequency from Table 102 by 4 to obtain `sysclk' frequency divide the frequency from Table 102 by 2 to obtain `sysclk' frequency
SAA7391
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDDD(core) VDDD(pad) VDDA Vi(max) Vo Io P Tstg Tamb 9 PARAMETER core digital supply voltage periphery digital supply voltage analog supply voltage maximum voltage on any input output voltage on any output output current (continuous) power dissipation storage temperature operating ambient temperature MIN. -0.5 -0.5 -0.5 -0.5 -0.5 - - -55 0 +4.5 +6.5 +4.6 VDDD(pad) + 0.5 +6.5 20 400 +125 70 TYP. V V V V V mA mW C C UNIT
THERMAL CHARACTERISTICS SYMBOL PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 55 UNIT K/W
Rthj-a
10 CHARACTERISTICS SYMBOL Digital Inputs INPUTS DESIGNATED BY `C' (CMOS VOLTAGE LEVELS) VIL VIH ILI Ci VIL VIH ILI Ci LOW-level input voltage HIGH-level input voltage input leakage current input capacitance Vi = 0 to VDDD(pad) -0.3 0.7VDDD(pad) -10 - -0.3 2.0 Vi = 0 to VDDD(pad) -10 - - - - - - - - - 0.3VDDD(pad) 10 10 V A pF VDDD(pad) + 0.3 V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
INPUTS DESIGNATED BY `T' (TTL VOLTAGE LEVELS) LOW-level input voltage HIGH-level input voltage input leakage current input capacitance 0.8 10 10 V A pF VDDD(pad) + 0.3 V
1997 Aug 01
67
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL
PARAMETER
CONDITIONS -
MIN. - - - -
TYP.
MAX.
UNIT
POR AND RESET (SCHMITT TRIGGER) Vth(pos) Vth(neg) Vhys Ci Schmitt trigger positive-going switching threshold voltage Schmitt trigger negative-going switching threshold voltage hysteresis voltage input capacitance 0.8VDDD(pad) - - 3 V V V pF
0.2VDDD(pad) 1.0 -
Digital Outputs OUTPUTS DESIGNATED BY `L' (CMOS LEVELS) VOL VOH CL to(r) to(f) LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time CL = 20 pF; 10% to 90% CL = 20 pF; 90% to 10% IOL = 2 mA IOH = -2 mA 0 VDDD(pad) - 0.4 - - - - - - - - 0.4 VDDD 20 10 10 V V pF ns ns
OUTPUTS DESIGNATED BY `M' (CMOS LEVELS) VOL VOH CL to(r) to(f) LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time CL = 20 pF; 10% to 90% CL = 20 pF; 90% to 10% IOL = 4 mA IOH = -4 mA 0 VDDD(pad) - 0.4 - - - - - - - - 0.4 VDDD 20 8 8 V V pF ns ns
OUTPUTS DESIGNATED BY `H' (CMOS LEVELS) VOL VOH CL to(r) to(f) LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time CL = 20 pF; 10% to 90% CL = 20 pF; 90% to 10% IOL = 8 mA IOH = -8 mA 0 VDDD(pad) - 0.4 - - - - - - - - 0.4 VDDD 20 6 6 V V pF ns ns
OUTPUTS: DESIGNATED BY `AL' (ATA DATA BUS LEVELS) VOL VOH CL to(r) to(f) LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time CL = 40 pF; 10% to 90% CL = 40 pF; 90% to 10% IOL = 4 mA IOH = -4 mA 0 2.4 - 5 5 - - - - - 0.4 VDDD 100 - - V V pF ns ns
1997 Aug 01
68
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - -
TYP.
MAX.
UNIT
OUTPUTS: DESIGNATED BY `AH' (ATA LEVELS) VOL VOH CL to(r) to(f) LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time CL = 40 pF; 10% to 90% CL = 40 pF; 90% to 10% IOL = 12 mA IOH = -4 mA 0 2.4 - 5 5 0.4 VDDD 100 - - V V pF ns ns
Crystal oscillator input: CRIN fCLK VIL VIH ILI Ci fxtal gm Ro Gv Cfb Co external clock frequency LOW-level input voltage HIGH-level input voltage input leakage current input capacitance 8 -0.3 0.7VDDD(core) -10 - - 16 - GV = gm x Ro 5 - - 8.4677 35 - - - - - - - - - - 0.3VDDD(core) VDDD(C) + 0.3 10 10 MHz V V A pF
Crystal oscillator output: CROUT crystal frequency transconductance output resistance small signal voltage gain feedback capacitance output capacitance 35 - - - 5 10 V/V pF pF MHz m
1997 Aug 01
69
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
11 TIMING CHARACTERISTICS 11.1 External memory interface timing
SAA7391
Table 104 DRAM interface timing (fast-page mode); see Figs 13 and 14 and note 1 SYMBOL Tcy tACC(CAS) tACC(RAS) tRASH tRASL th(RAS) tCASL th(CAS) td(CASH-RAS) td(RAS-CAS) td(RAS-CA) tsu(RA) th(RA) tsu(CA) th(CA) th(CA-RASL) tl(CA-RAS) th(R) th(R-RAS) tsu(W) th(W) tWL th(W-RAS) tl(W-CAS) tl(W-RAS) tsu(DO) th(DO) th(DO-RAS) Note 1. For further information regarding the DRAM timing please consult the device user manual or contact product support. PARAMETER read or write cycle period access time from CAS access time from RAS RAS HIGH time RAS LOW time RAS hold time CAS LOW time CAS hold time delay time CAS HIGH to RAS RAS to CAS delay time RAS to column address delay time row address set-up time row address hold time column address set-up time column address hold time column address hold time from RAS LOW column address to RAS lead time read command hold time read command hold time from RAS write command set-up time write command hold time write command LOW time write command hold time from RAS write command to CAS lead time write command to RAS lead time data output set-up time data output hold time data output hold time from RAS CONDITIONS - - 70 80 20 20 80 10 25 20 0 15 0 20 60 40 0 60 0 15 15 60 20 20 0 15 60 MIN. 160 - 20 - - 10000 - 10000 - - - - - - - - - - - - - - - - - - - - - MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1997 Aug 01
70
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
Tcy tRASL th(CA-RASL) XRAS th(CAS) td(RAS-CAS) td(CASH-RAS) XCAS td(RAS-CA) th(RA) tsu(RA) XDA0 to XDA13 ROW tsu(W) th(W) tWL XWR th(W-RAS) tl(W-RAS) tl(W-CAS) th(DO-RAS) tsu(DO) th(DO) th(CA) tsu(CA) COLUMN tl(CA-RAS) th(RAS) tCASL td(CASH-RAS) tRASH
XDD0 to XDD7
MGK518
Fig.13 External DRAM write cycle timing for fast-page.
1997 Aug 01
71
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
Tcy tRASL th(CA-RASL) XRAS th(CAS) td(RAS-CAS) td(CASH-RAS) XCAS td(RAS-CA) th(RA) tsu(RA) XDA0 to XDA13 ROW th(CA) tsu(CA) COLUMN th(R) th(R-RAS) XWR tACC(RAS) tACC(CAS) XDD0 to XDD7 INPUT
MGK519
tRASH
th(RAS) tCASL
td(CASH-RAS)
tl(CA-RAS)
Fig.14 External DRAM read cycle timing for fast-page.
1997 Aug 01
72
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
11.2 Host interface timing
SAA7391
This section deals with the implemented timings of the SAA7391 host interface in both the ATAPI and generic interface modes. The timings of the ATAPI PIO Mode 3 and Mode 4 are also taken into account. Table 105 Basic AC characteristics, ATA bus SYMBOL tr tf Ci Co 11.2.1 PARAMETER rise time for any signal on ATAPI interface fall time for any signal on ATAPI interface input capacitance for each host or device output capacitance for each host or device HOST INTERFACE ATAPI PIO AND DMA TIMING CONDITIONS 10 to 90% of full signal amplitude with a total capacitive load of 100 pf 10 to 90% of full signal amplitude with a total capacitive load of 100 pf MIN. 5 5 - - MAX. - - 25 25 UNIT ns ns pf pf
This section deals with the implemented timings of the SAA7391 host interface in both the ATAPI and generic interface modes. The timings of the ATAPI PIO Mode 3 and Mode 4 are also taken into account (see Table 105).
1997 Aug 01
73
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
11.2.2 ATA BUS TIMING
SAA7391
The figures and timing characteristics detail the timing as specified in the ATA-3 documentation. Table 106 Timing of PIO data transfer to and from device; see Fig.15 SYMBOL Tcy cycle time PARAMETER note 1 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 tsu(A-DIOR/DIOW) address valid to DIOR/DIOW set-up time Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 tW(DIOR/DIOW) DIOR/DIOW pulse width 16-bit; note 1 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 8-bit; note 1 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 trec(DIOR/DIOW) DIOR/DIOW recovery time note 1 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 tsu(DIOW) DIOW data set-up time Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 - - - 70 25 60 45 30 30 20 - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns 290 290 290 80 70 - - - - - ns ns ns ns ns 165 125 100 80 70 - - - - - ns ns ns ns ns 600 383 240 180 120 70 50 30 30 25 - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns CONDITIONS MIN. MAX. UNIT
1997 Aug 01
74
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL th(DIOW)
PARAMETER DIOW data hold time
CONDITIONS Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
MIN. 30 20 15 10 10 50 35 20 20 20 5 5 5 5 5 - - - - - - - - - - - - - - - 20 15 10 10 10 - - - - - - - - - - - - - - -
MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(DIOR)
DIOR data set-up time
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
th(DIOR)
DIOR data hold time
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
tz(DIOR)
DIOR data 3-state
note 2 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 30 30 30 30 30 90 50 40 - - 60 45 30 - - - - - - -
tass(A-IOCS16)
address valid to IOCS16 assertion time
note 3 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
trel(A-IOCS16)
address valid to IOCS16 released time
note 3 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
th(DIOR/DIOW-A)
DIOR/DIOW to address valid hold time
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
1997 Aug 01
75
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL tR(DAT-IORDY)
PARAMETER read data valid to IORDY active (if IORDY initially LOW after tsu(IORDY))
CONDITIONS Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 0 0 0 0 0
MIN. - - - - - - - - - -
MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(IORDY)
IORDY set-up time
note 4 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 35 35 35 35 35 - - - - -
tW(IORDY)
IORDY pulse width
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
1250 1250 1250 1250 1250
Notes 1. Tcy is the minimum total cycle time, tW(DIOR/DIOW) is the minimum command active time, and trec(DIOR/DIOW) is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of Tcy, tW(DIOR/DIOW), and trec(DIOR/DIOW) shall be met. The minimum total cycle time requirements is greater than the sum of tW(DIOR/DIOW) and trec(DIOR/DIOW). This means a host implementation can lengthen either or both tW(DIOR/DIOW) or trec(DIOR/DIOW) to ensure that Tcy is equal to or greater than the value reported in the devices identify drive data. A device implementation shall support any legal host implementation. 2. This parameter specifies the time from the negation edge of DIOR to the time that the data bus is no longer driven by the device (3-state). 3. The delay from the activation of DIOR or DIOW until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device is not driving IORDY negated at the tsu(IORDY) after the activation of DIOR or DIOW, then tsu(DIOR) shall be met and tR(DAT-IORDY) is not applicable. If the device is driving IORDY negated at the time tsu(IORDY) after the activation of DIOR or DIOW, then tR(DAT-IORDY) shall be met and tsu(DIOR) is not applicable. 4. tass(A-IOCS16) and trel(A-IOCS16) apply only to Modes 0, 1 and 2. This signal is not valid for other modes.
1997 Aug 01
76
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
Tcy address valid tsu(A-DIOR/DIOW) tW(A-DIOR/DIOW) DIOR/DIOW th(DIOR/DIOW-A) trel(A-IOCS16) trec(A-DIOR/DIOW)
write DD0 to DD15 tsu(DIOW) read DD0 to DD15 th(DIOR) tass(A-IOCS16) IOCS16 tsu(DIOR) tz(DIOR) th(DIOW)
IORDY no wait tsu(IORDY) IORDY ignoring glitch tR(DAT-IORDY) IORDY causing wait tW(IORDY)
MGK520
Fig.15 ATA bus timing diagram.
1997 Aug 01
77
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 107 Single word DMA timing; see Fig.16 SYMBOL Tcy PARAMETER cycle time CONDITIONS Mode 0 Mode 1 Mode 2 td(DMACK-DMARQ) DMACK to DMARQ delay Mode 0 Mode 1 Mode 2 tW(DIOR/DIOW) DIOR/DIOW pulse width 16-bit Mode 0 Mode 1 Mode 2 tACC(DIOR) DIOR data access time Mode 0 Mode 1 Mode 2 th(DIOR) DIOR data hold time Mode 0 Mode 1 Mode 2 tsu(DIOW) DIOW data set-up time Mode 0 Mode 1 Mode 2 th(DIOW) DIOW data hold time Mode 0 Mode 1 Mode 2 tsu(DMACK-DIOR/DIOW) DMACK to DIOR/DIOW set-up time Mode 0 Mode 1 Mode 2 th(DIOR/DIOW-DMACK) DIOR/DIOW to DMACK hold time Mode 0 Mode 1 Mode 2 tsu(DIOR) DIOR set-up time Mode 0 Mode 1 Mode 2 960 480 240 - - - 480 240 120 - - - 5 5 5 250 100 35 50 30 20 0 0 0 0 0 0 MIN. - - - 200 100 80 - - - 250 150 60 - - - - - - - - - - - - - - -
SAA7391
MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tW(DIOR/DIOW) - tACC(DIOR) - tW(DIOR/DIOW) - tACC(DIOR) - tW(DIOR/DIOW) - tACC(DIOR) -
1997 Aug 01
78
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
Tcy
DMARQ td(DMACK-DMARQ) DMACK tsu(DMACK-DIOR/DIOW) DIOR/DIOW tACC(DIOR) read DD0 to DD15 tsu(DIOW) write DD0 to DD15
MGK521
tW(DIOR/DIOW)
th(DIOR/DIOW-DMACK)
tsu(DIOR)
th(DIOR)
th(DIOW)
Fig.16 ATA single word DMA timing.
1997 Aug 01
79
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
Table 108 Multi-word DMA timing; see Fig.17 SYMBOL Tcy cycle time PARAMETER CONDITIONS note 1 Mode 0 Mode 1 Mode 2 tW(DIOR/DIOW) DIOR/DIOW pulse width 16-bit Mode 0 Mode 1 Mode 2 tACC(DIOR) DIOR data access time Mode 0 Mode 1 Mode 2 th(DIOR) DIOR data hold time note 2 Mode 0 Mode 1 Mode 2 tsu(DIOW) DIOW data set-up time Mode 0 Mode 1 Mode 2 th(DIOW) DIOW data hold time Mode 0 Mode 1 Mode 2 tsu(DMACK-DIOR/DIOW) DMACK to DIOR/DIOW set-up time Mode 0 Mode 1 Mode 2 th(DIOR/DIOW-DMACK) DIOR/DIOW to DMACK hold time Mode 0 Mode 1 Mode 2 tWneg(DIOR) DIOR negated pulse width note 1 Mode 0 Mode 1 Mode 2 tWneg(DIOW) DIOW negated pulse width note 1 Mode 0 Mode 1 Mode 2 td(DIOR-DMARQ) delay time from DIOR to DMARQ Mode 0 Mode 1 Mode 2 td(DIOW-DMARQ) delay time from DIOW to DMARQ Mode 0 Mode 1 Mode 2 1997 Aug 01 80 215 50 25 - - - - - - - - - 120 40 35 40 40 35 50 50 25 - - - 5 5 5 100 30 20 20 15 10 0 0 0 20 5 5 - - - - - - - - - - - - - - - 480 150 120 215 80 70 - - - - - - - - - 150 60 - MIN.
SAA7391
MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL td(DMACK-z)
PARAMETER delay time from DMACK to 3-state
CONDITIONS note 2 Mode 0 Mode 1 Mode 2 - - -
MIN.
MAX. 20 25 25
UNIT ns ns ns
Notes 1. Tcy is the minimum total cycle time, tW(DIOR/DIOW) is the minimum command active time, and tWneg(DIOR) or tWneg(DIOW), as appropriate) is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of Tcy, tW(DIOR/DIOW) and tWneg(DIOR) or tWneg(DIOW) shall be met. The minimum total cycle time requirement, Tcy, is greater than the sum of tW(DIOR/DIOW) and tWneg(DIOR) or tWneg(DIOW). This means a host implementation can lengthen either or both tW(DIOR/DIOW) or tWneg(DIOR) or tWneg(DIOW) to ensure that Tcy is equal to the value reported in the devices identify drive data. A device implementation shall support any legal host implementation. 2. The original ATA standard defined a maximum value for th(DIOR). The meaning of this value was not clear. This parameter has been renamed to td(DMACK-z) and specifies the time from the negation edge of DMACK to the time the device data signals are no longer driven by the device (3-state). The td(DMACK-z) parameter applies only at the end of a multi-word DMA cycle, i.e., when DMACK is negated. The device may actively drive the Device Data signals, or may 3-state the device data signals, while DMACK is active from the first time that DIOR is asserted until DMACK is negated as long as tACC(DIOR) and th(DIOR) requirements are met.
1997 Aug 01
81
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
Tcy
DMARQ td(DIOR-DMARQ) DMACK
(1)
tsu(DMACK-DIOR/DIOW) th(DIOR/DIOW-DMACK) tsu(DIOW) tW(DIOR/DIOW) DIOR/DIOW tWneg(DIOR) th(DIOR)
tACC(DIOR) read DD0 to DD15 tWneg(DIOW)
td(DMACK-z)
th(DIOW) write DD0 to DD15
MGK522
(1) This signal may be negated by the host to suspend the DMA transfer in progress. For multi-word DMA transfers, the device may negate DMARQ within the td(DIOR-DMARQ) or td(DIOW-DMARQ) specified time once DMACK is asserted and reassert it again at a later time to resume the DMA operation. Alternatively, if the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK.
Fig.17 Multi-word DMA timing.
1997 Aug 01
82
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
11.2.3 ULTRA DMA OPERATION AND TIMING
SAA7391
Selection of ultra DMA is similar to multi-word DMA operation. Bits 5, 6 and 7 of the DTCTR register should all be set to logic 1 and data byte counts and data flow selection does not change from ATAPI DMA operation. The `ultra_stop' interrupt (IFSTAT bit 4) when enabled by `ultra_stopien' (IFCTRL bit 4) will interrupt the microcontroller if the host stops a transfer before the required data has been transfer i.e. the data byte count has not reached zero. A flag, `crc_error' (IFSTAT bit 0) if asserted in conjunction with the `dtei' interrupt (IFSTAT bit 6) will indicate to the microcontroller that the last transfer of data was corrupt. No changes of pin direction are required for ultra DMA, but the ATA description changes (see Table 109). Table 109 Ultra DMA pin changes ATA PIN NAME ULTRA DMA READ PIN NAME ULTRA DMA WRITE PIN NAME IORDY DMARQ DMACK sender strobe DMARQ DMACK D_DMARDY (device DMA ready) DMARQ DMACK COMMENT D_DMARDY can be used to pause transmission similar to ATAPI DMA similar to ATAPI DMA, but also used at the end of transmission for the CRC strobe stop can terminate the data transfer before all bytes have been transferred; this action will generate a microcontroller interrupt H_DMARDY can be used by to pause transmission
DIOR
STOP
sender strobe
DIOW
H_DMARDY (host DMA ready) STOP
11.2.4
ULTRA DMA READ/WRITE TIMING
This section provides the timing diagrams for the ultra DMA protocol. The timing diagrams are shown in Figs 18 to 27. The timing information is provided in Table 110. Table 110 Timing parameter values; see Figs 18 to 27 SYMBOL Tcy PARAMETER cycle time (from STROBE edge to STROBE edge) CONDITIONS Mode 0 Mode 1 Mode 2 tsu(D)(RX) data set-up time (at receiver) Mode 0 Mode 1 Mode 2 th(D)(RX) data hold time (at receiver) Mode 0 Mode 1 Mode 2 tsu(DV) data valid set-up time (at sender); time from data bus being valid until STROBE edge Mode 0 Mode 1 Mode 2 1997 Aug 01 83 MIN. 117 77 57 15 10 7 3 3 3 75 48 38 MAX. - - - - - - - - - - - - UNIT ns ns ns ns ns ns ns ns ns ns ns ns
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL th(DV)
PARAMETER data valid hold time (at sender); time from STROBE edge until data goes invalid
CONDITIONS Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 8 8 8 0 0 0
MIN.
MAX. - - - 150 150 150 150 150 150 - - - 10 10 10 - - - 70 70 70 50 30 20 75 60 50 - - - 20 20 20 - - - - - -
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tli
limited interlock time; time allowed between an action by one agent and the following action by the other agent limited interlock time with minimum
tli(min)
20 20 20 0 0 0 - - - 20 20 20 20 20 20 - - - - - - 160 125 100 - - - 0 0 0 20 20 20
tui
unlimited interlock time
Mode 0 Mode 1 Mode 2
t(O-z)(max)
maximum time allowed for outputs to 3-state
Mode 0 Mode 1 Mode 2
td(min)
minimum delay time for output drivers turning on (from high-impedance)
Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2
tenv
envelope time (all control signal transitions are within the DACKb envelope by this time)
tres(STROBE-DMARDY)
STROBE-to-DMARDY response time to ensure synchronous pause case (when receiver is pausing) READY-to-final-STROBE time (this long after DMARDYb de-assertion, no more STROBE edges may be sent) READY-to-pause time: time until a receiver may assume that the sender has paused after de-asserting DMARDYb pull-up time before allowing IORDY to go high-impedance
t(READY-STROBE)
t(READY-PAUSE)
tpu
t(IORDY)(max)
maximum time driver must wait before driving IORDY
tsu(ass/deass)
set-up time before assertion and de-assertion of DACKb
1997 Aug 01
84
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
SYMBOL th(ass/deass)
PARAMETER hold time before assertion and de-assertion of DACKb
CONDITIONS Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2
MIN. 20 20 20 50 50 50
MAX. - - - - - -
UNIT ns ns ns ns ns ns
tss(STROBE-STOP)
time from STROBE edge to negation of DMARQ or assertion of STOP
handbook, full pagewidth
Tcy tsu(DV)
Tcy tsu(DV)
strobe at sender th(DV) data at sender tsu(D)(RX) th(D)(RX) strobe at receiver th(D)(RX) tsu(D)(RX) th(D)(RX) th(DV) th(DV)
data at receiver
MGK523
Fig.18 Sustained synchronous DMA burst timing diagram.
handbook, halfpage
STROBE (host) tss(STROBE-STOP) STOP
MGK524
Fig.19 Host stop request (write command).
1997 Aug 01
85
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, halfpage
STROBE (drive) tss(STROBE-STOP) DRQ
MGK525
Fig.20 Drive stop request (read command).
handbook, full pagewidth
DRQ (drive)
tui DACKb (host) tsu(ass/deass) tenv STOP (host) tsu(ass/deass) tenv DMARDY (host) tli t(IORDY)(max) STROBE (drive) td(min) t(O-z)(max) DATA (drive) tsu(ass/deass) DA and CS
MGK526
tli
tsu(DV) th(DV)
Fig.21 Drive initiating a DMA burst for a write command.
1997 Aug 01
86
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth DRQ (drive)
tui DACKb (host) th(ass/deass) tenv STOP (host) t(IORDY)(max) DMARDY (drive) tui STROBE (host) tsu(DV) th(DV) DATA (host) th(ass/deass) DA and CS
MGK527
tli
Fig.22 Receiver pausing a DMA burst.
1997 Aug 01
87
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
t(READY-PAUSE)
DRQ (drive)
DACKb (host) t(READY-PAUSE) STOP (host) tres(STROBE-DMARDY) DMARDYb t(READY-STROBE) STROBE
DATA
MGK528
Fig.23 Receiver pausing a DMA burst.
1997 Aug 01
88
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
DRQ (drive) tli(min) tsu(DV) DACKb (host) tli STOP (host) tli DMARDYb (host) tli STROBE (drive) t(O-z)(max) DATA (drive) td(min) DA and CS
MGK529
tsu(ass/deass)
tsu(ass/deass)
t(IORDY)(max)
th(DV) CRC tsu(ass/deass)
Fig.24 Drive terminating a DMA burst during a read command.
1997 Aug 01
89
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
DRQ (drive) tli(min) tli(min) DACKb (host) tli STOP (host) tsu(DV) tsu(ass/deass)
t(IORDY)(max)
DMARDYb (drive) tli tsu(ass/deass) STROBE (host) th(DV) DATA (host) CRC tsu(ass/deass) DA and CS
MGK530
Fig.25 Drive terminating a DMA burst during a write command.
1997 Aug 01
90
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
tli
DRQ (drive) tli(min) tli(min) tsu(DV) DACKb (host) tsu(ass/deass) STOP (host) t(IORDY)(max) DMARDYb (host) tli tsu(ass/deass) STROBE (drive) td(min) t(O-z)(max) DATA (drive) CRC tsu(ass/deass) DA and CS
MGK531
th(DV)
Fig.26 Host terminating a DMA burst during a read command.
1997 Aug 01
91
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
tli
DRQ (drive) tli(min) tsu(DV) DACKb (host) tsu(ass/deass) STOP (host) tli DMARDYb (drive) tli STROBE (host) th(DV) DATA (host) CRC tsu(ass/deass) DA and CS
MGK532
t(IORDY)(max)
tsu(ass/deass)
Fig.27 Host terminating a DMA burst during a write command.
11.3
Sub-CPU interface timing
Table 111 Timing parameter values for Figs 28 and 29 SYMBOL tAVLL tRLDV tW(ALE) th(A) tDVWL Note 1. tCLCL = the SAA7391 system clock period. PARAMETER address valid to ALE LOW RD LOW to valid data in ALE pulse width address hold time DATA valid before WR LOW 10 - 35 10 0 MIN. - 7tCLCL + - - - 20(1) MAX. UNIT ns ns ns ns ns
1997 Aug 01
92
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
SAA7391
handbook, full pagewidth
tW(ALE) th(A)
tRLDV
ALE
RD
PORT 0
A0 to A7
DATA IN
A0 to A7
PORT 2
A8 to A15
MGL165
Fig.28 Timing diagram for an 8051 microcontroller interface read cycle.
handbook, full pagewidth
tAVLL tDVWL
ALE
WR
PORT 0
A0 to A7
DATA OUT
A0 to A7
PORT 2
A8 to A15
MGL166
Fig.29 Timing diagram for an 8051 microcontroller interface write cycle.
1997 Aug 01
93
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
11.4 UART timing
SAA7391
handbook, full pagewidth
10 x period (80 to 320 s) idle 0 1 2 3 4 5 6 7 P next start may be here
STOP parity data START
MGK614
See Section 7.9 for relevant timing.
Fig.30 Timing diagram of byte transmission of UART in asynchronous mode.
handbook, full pagewidth SPI ACK
txfull
rxfull
SPI clock
SerIn, SerOut
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
'erln' samples
MGK615
See Section 7.9 for relevant timing.
Fig.31 Timing diagram of SPI mode, byte transmission of UART in synchronous mode.
1997 Aug 01
94
1997 Aug 01 95
Philips Semiconductors
12 APPENDIX A
ATAPI CD-R block encoder/decoder
Table 112 The SAA7391 register map ADDRESS FF00H FF01H FF02H FF03H FF04H FF05H FF06H FF07H FF08H FF09H FF0AH FF0BH FF0CH FF0DH FFOEH FF0FH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH NAME HEAD0 HEAD1 HEAD2 HEAD3 SUBHEAD0 SUBHEAD1 SUBHEAD2 SUBHEAD3 STAT0 STAT1 STAT2 STAT3 STAT4 CTRL0 CTRL1 CTRL2 IFCONFIG C1BLERCNT C2BLERCNT SUBMODETX MMAUD MCK_CON MMCTRL SUBMODERX SUBPAGE1-H SUBPAGE1-L SUBPAGE2-H SUBPAGE2-L ACCESS R R R R R R R R R R R R R W W W W R R W W W W W W W W W BLOCK drive drive - - - - - - - - - - - - - - drive - - - - - - - - - - - 16 NUMBER OF BITS 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 see Table 32 see Table 89 see Table 30 see Table 35 see Table 12 see Table 97 see Table 16 COMMENT see Table 20 ELM `NEAR EQUIVALENT' REGISTER HEAD0 HEAD1 HEAD2 HEAD3 SHEAD0 SHEAD1 SHEAD2 SHEAD3 STAT0 STAT1 STAT2 STAT3 STAT3 CTRL0 CTRL1 CTRL1 IFCONFIG - - - - - - - - - - - CHAUCER `NEAR EQUIVALENT' REGISTER - - - - - - - - - - - - - - - - FECTRL - - - - - - - PAGEREG PAGEREG - -
Objective specification
SAA7391
1997 Aug 01 96
Philips Semiconductors
ADDRESS FF1CH FF1DH FF1EH FF1FH FF20H FF21H FF22H FF23H FF24H FF25H FF26H FF27H FF28H FF29H FF2AH FF2BH FF2CH FF2DH FF2EH FF2FH FF30H FF31H FF32H FF33H FF34H FF35H
NAME SUBSEG1-H SUBSEG1-L - - DRIVECURSEG-H DRIVECURSEG-L DRIVEPREVSEG-H DRIVEPREVSEG-L DRIVEOFFSET-H DRIVEOFFSET-L DRIVENEXTSEG-H DRIVENEXTSEG-L AUXSEGMENT-H AUXSEGMENT-L SUBPOINTR-H SUBPOINTR-L SUBBASEPOINTR-H SUBBASEPOINTR-L SUBPOINTW-H SUBPOINTW-L SUBBASEPOINTW-H SUBBASEPOINTW-L CDDA-H CDDA-L DAOFFSET-H DAOFFSET-L
ACCESS W W - - RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
BLOCK - - - - - - - - - - - - - - - - - - - - - - - - - -
NUMBER OF BITS 16 - - 16 16
COMMENT see Table 90 - - see Table 14
ELM `NEAR EQUIVALENT' REGISTER - - - - - - - -
CHAUCER `NEAR EQUIVALENT' REGISTER MICFRM# MICFRM# - - FEFRM# FEFRM# LASTCMPFM/EC CFRM FEFRMOFF FEFRMOFF - - - - - - - - - - - - - - - - -
ATAPI CD-R block encoder/decoder
16 16 16 16 16 16 16 16 16 see Table 35 see Table 14 see Table 29 see Table 34
- - - - - - - - - - SUB-H SUB-L SUB-H SUB-L - - - -
Objective specification
SAA7391
1997 Aug 01 97
Philips Semiconductors
ADDRESS FF36H FF37H FF38H FF39H FF3AH FF3BH FF3CH FF3DH FF3EH FF3FH FF40H FF41H FF42H FF43H FF44H FF45H FF46H FF47H FF48H FF49H FF4AH FF4BH FF4CH FF4DH FF4EH FF4FH
NAME COPYFROMOFFSET-H COPYFROMOFFSET-L COPYTOOFFSET-H COPYTOOFFSET-L COPYFROMSEG-H COPYFROMSEG-L COPYTOSEG-H COPYTOSEG-L FROM2OFFSET-H FROM2OFFSET-L TO2OFFSET-H TO2OFFSET-L HOSTBYTEOFFSET-H HOSTBYTEOFFSET-L HOSTCURSEG-H HOSTCURSEG-L - - - - SPI_RX_OFF-H SPI_RX_OFF-L SPI_TX_OFF-H SPI_TX_OFF-L - -
ACCESS RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW - - - - RW RW RW RW - -
BLOCK - - - - - - - - - - - - - - - - - - - - - - - - - -
NUMBER OF BITS
COMMENT see Table 42
ELM `NEAR EQUIVALENT' REGISTER -
CHAUCER `NEAR EQUIVALENT' REGISTER - - - - - - - - - - - - - - SCSICFRM SCSICFRM - - - - - - - - - -
ATAPI CD-R block encoder/decoder
16 16
- - - - - -
16 16 16 16 - - - - 16 16 - - - - - - - - see Table 93 see Table 85
- - - - DAC DAC DAC DAC - - - - - - - - - -
Objective specification
SAA7391
1997 Aug 01 98
Philips Semiconductors
ADDRESS FF50H FF51H FF52H FF53H FF54H FF55H FF56H FF57H FF58H FF59H FF5AH FF5BH FF5CH FF5DH FF5EH FF5FH FF60H FF61H FF62H FF63H FF64H FF65H FF66H FF67H FF68H FF69H FF6AH FF6BH FF6CH FF6DH
NAME HOSTSUBBLKOFFSET2-H HOSTSUBBLKOFFSET2-L HOSTSUBBLKCOUNT2-H HOSTSUBBLKCOUNT2-L HOSTNEXTSEG-H HOSTNEXTSEG-L HOSTRELOADFLAGS HOSTNEXTSEGCOUNT HOSTSUBBLKOFFSET0-H hostsubblkoffset0-L HOSTSUBBLKCOUNT0-H HOSTSUBBLKCOUNT0-L HOSTSUBBLKOFFSET1-H HOSTSUBBLKOFFSET1-L HOSTSUBBLKCOUNT1-H HOSTSUBBLKCOUNT1-L DRIVECURCOUNT DRIVENEXTCOUNT COPYCOUNT-H COPYCOUNT-L HOSTBYTECOUNT-H HOSTBYTECOUNT-L HOSTCURSEGCNT COPYCONTROL HOSTRELSEG-H HOSTRELSEG-L DRAM_CONFIG AUX_FORM_SCAN - -
ACCESS RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W RW - -
BLOCK - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NUMBER OF BITS 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 16 8 8 - -
COMMENT see Table 85
ELM `NEAR EQUIVALENT' REGISTER - - - - - - - - - - - - - - - -
CHAUCER `NEAR EQUIVALENT' REGISTER - - - - SCSISFRM SCSISFRM - - - - - - - - - - - - - - - - - - - -
ATAPI CD-R block encoder/decoder
see Table 14 see Table 42 see Table 85
- - - - - - -
see Table 42 see Table 85 see Table 90 see Table 85 - -
- - - MEMS - - -
Objective specification
SAA7391
DRAMSEL - - -
1997 Aug 01 99
Philips Semiconductors
ADDRESS FF6EH FF6FH
NAME - TEMP_DATA
ACCESS - RW
BLOCK - -
NUMBER OF BITS - 8
COMMENT - holding register; see Section 7.6 see Table 35 - see Table 98 see Table 93
ELM `NEAR EQUIVALENT' REGISTER - -
CHAUCER `NEAR EQUIVALENT' REGISTER - -
ATAPI CD-R block encoder/decoder
FF70H FF71H FF72H FF73H FF74H FF75H FF76H FF77H FF78H FF79H FF7AH
IECCTRL IECCAT - CONF_8051 UART_PRESCALER UART_DMA_CTRL UARTCOM RXDATA/TXDATA UARTINTSTAT/RESET UARTINTENABLE INT1STAT/RESET
W W - W RW RW W RW RW W RW
- - - - - - - - - - -
8 8 - 8 8 8 8 8 8 8 8
- - - - - - - - - -
- - - - - BRGSEL - SERCOM - - -
see Tables 45 and 46 see Table 47 see Tables 48 and 49 see Table 50 see Table 93
-
FF7BH FF7CH
INT1ENABLE INT2STAT/RESET
W RW
- -
8 8
- -
- -
FF7DH FF7EH FF7FH
INT2ENABLE UARTSTAT UARTAUXSTAT
W R R
- - -
8 8 8
- - -
- - -
Objective specification
SAA7391
1997 Aug 01 100
Philips Semiconductors
ADDRESS FF80H FF81H FF82H FF83H FF84H FF85H FF86H FF87H FF88H FF89H FF8AH FF8BH FF8CH FF8DH FF8EH FF8FH FF90H FF91H FF92H FF93H FF94H FF95H FF96H FF97H FF98H FF99H FF9AH FF9BH FF9CH FF9DH
NAME ADATA IFCTRL DBCL DBCH DTRG DTACK RESET ASTAT ITRG ADRADR ASAMT DTCTR ADRSEL AINTR AERR ACMD ADCTR AFEAT IFSTAT APCMD HICONF0 HICONF1 HISEQ SHSTAT SHERR HIDEV HISTAT
ACCESS RW RW RW RW W W W RW W W RW RW RW RW RW R R R RW R RW RW RW RW RW RW R
BLOCK - - - - - - - - - - - - - - - - - - - - - - - - - - -
NUMBER OF BITS 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
COMMENT see Table 56
ELM `NEAR EQUIVALENT' REGISTER ADATA IFCTRL DBCL DBCH DTRG DTACK RESET ASTAT ITRG ADRADR ASAMT DTCTR ADRSEL AINTR AERR ACMD ADCTR AFEAT IFSTAT APCMD - - - - - - -
CHAUCER `NEAR EQUIVALENT' REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - -
ATAPI CD-R block encoder/decoder SAA7391
Objective specification
-
3 unused address locations
1997 Aug 01 101
Philips Semiconductors
ADDRESS FF9EH FF9FH FFA0H FFA1H FFA2H FFA3H FFA4H FFA5H FFA6H FFA7H FFBFH FFC0H FFDFH FFE0H FFFFH
NAME MULTI_CON CLK_CON TRANSFERCOUNT (7 to 0) TRANSFERCOUNT (15 to 8) TRANSFERCOUNT (23 to 16) TRANSFERCOUNT (31 to 24) PACKETSIZE_STORE(L) PACKETSIZE_STORE(H) SEQUENCER_STATUS
ACCESS - - RW RW RW RW RW RW R
BLOCK - - - - - - - - -
NUMBER OF BITS 8 32
COMMENT see Table 100 see Table 56
ELM `NEAR EQUIVALENT' REGISTER - - - - - -
CHAUCER `NEAR EQUIVALENT' REGISTER - CLKSEL - - - - - - -
ATAPI CD-R block encoder/decoder
16 8
- - -
25 unused address locations 32 generic addresses in 3-state locations 32 3-state address locations
Objective specification
SAA7391
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
13 APPLICATION INFORMATION
SAA7391
handbook, full pagewidth
CACHE RAM
IEC 958 CD-DSP CD7 ACE CD65 HD61 I2S-bus I2S-bus DAC
DISC
SAA7391
IDE connector
SERVO
Q-W
CD ENGINE I2S-bus CD-R ENCODER (P, Q) R-W INT1, INT2 ALE PSEN R/W synch/S2B 8051 MICROCONTROLLER ROM I2C-bus
GENERIC/ NCR CONTROLLER
multiplexed address/data bus
MICROCONTROLLER
MGK507
Fig.32 Schematic diagram of SAA7391 in a typical application.
1997 Aug 01
102
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
14 PACKAGE OUTLINE LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
SAA7391
SOT486-1
c
y X
A 108 109 73 72 ZE
e Q E HE A A2 A1 (A 3) Lp L detail X 37 1 wM D HD ZD B vM B 36 bp vM A
wM bp pin 1 index 144
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.50 HD HE L 1.0 Lp 0.75 0.45 Q 0.69 0.59 v 0.2 w 0.1 y 0.1 Z D(1) Z E(1) 1.40 1.10 1.40 1.10 7 0o
o
22.15 22.15 21.85 21.85
ISSUE DATE 97-07-02
1997 Aug 01
103
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
15 SOLDERING 15.1 Introduction
SAA7391
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 15.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
1997 Aug 01
104
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7391
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Aug 01
105
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
NOTES
SAA7391
1997 Aug 01
106
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
NOTES
SAA7391
1997 Aug 01
107
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/01/pp108
Date of release: 1997 Aug 01
Document order number:
9397 750 01998

▲Up To Search▲

Price & Availability of SAA7391

	To Download SAA7391 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .